Datasheet LAN8023 (Microchip)

LAN8023 Dual 1G/10G/25G 1588 Optical Ethernet PHY Transceiver Highlights
• Two 1G/10G/25G serial Host interfaces • MAC Retimer (Ethernet serial PHY with 1588 - IEEE 802.3-2018 compliant mode) - Backplane Ethernet with KR/RS FEC - Ful y configurable Ethernet MAC and PHY on Host • Two 1G/10G/25G serial Line interfaces and Line - IEEE 802.3-2018 compliant - Host and Line must be of the same speed (e.g., 25G Ethernet), but can be of dif erent formats - SFP, XFP, SFP+, QSFP+, SFP28 & QSFP28 (e.g., KR FEC on Host and FEC on Line) • Integrated cross-connect features - Host and Line may be ful y synchronous or may - Any line port connectible to any host port have PPM clock dif erences handled by rate adap- - 1:1 and 1+1 host redundancy tation • IEEE 1588 and 802.1AS timestamping - IEEE 1588 timestamping and Synchronous Ether- • TSN frame preemption net support - TSN Frame Preemption support • PCS and MAC retimer modes • IEEE 802.3-2018 support for: • 256-BALL HFC-BGA (14 x 14 mm) - 1000BASE: KX, SX, LX • Extended temperature range - 10GBASE: “CR”, KR, SR, LR, ER -40°C (TA) to +110°C (TJ) -KR: KR FEC, ANEG, Training - 25GBASE: CR, CR-S, KR, KR-S, SR, LR, ER
Target Applications
-KR FEC, RSE FEC,ANEG, Training • 5G Smal Cel (up to class D requirements) • Loopback support • Industrial • Diagnostics - RX Eye Monitor plot • Enterprise IT - PRBS generator/checker • Broadband • Support for jumbo frames up to 10 KB (10,240 bytes)
Key Benefits
• PHY Management Interface is MDIO or SPI • IEEE 1588 -2008/2019 and 802.1AS -2011/2020 - High-speed SPI can be used simultaneously with - Supporting ITU-T G.8273.2 Classes C and D and MDIO to support high-bandwidth IEEE 802.1CM-2018 Category A+ management needs of 1588 - Highly flexible classification engine supports com- • Pin-strapping options binations of Ethernet, IPv4, IPv6, UDP, MPLS and • 40 GPIOs which alternately support: Pseudowire. Multiple flows per port are supported. - Two-wire Module Management Interface per port - Support for OC (PTP TimeTransmitter and Tim- - Two chip Interrupts eReceiver), BC and TC (one-step and two-step) - Two LEDs (Link, Activity) per port - 1PPS In/Out, with flexible TOD Load options • Coma mode support to eliminate port link bounc- - Timestamped 1588 frames can be Express frames or non-fragmented Preemptible frames ing at startup and to synchronize LEDs • PCS Retimer mode (Ethernet serial PHY w/ 1588) • Power down and power saving modes - Ful y configurable Ethernet PHY on Host and Line • Reference clock inputs - Host and Line must be of same speed but can be - System Reference Clock of dif erent formats - 1588 Reference Clock (e.g. Host is Backplane Ethernet with KR FEC, • Synchronous Ethernet support Line is Optical Ethernet with RS FEC) - Two recovered clock outputs, each selectable to be - Host and Line may be synchronous or may have from any Line recovered clock PPM clock dif erences handled by rate adaptation - Recovered clock outputs are optional y squelched - IEEE 1588 timestamping and Synchronous when the applicable clock is deemed unreliable Ethernet support • JTAG support - TSN Frame Preemption support  2025 Microchip Technology Inc. and its subsidiaries DS00006161B-page 1 Document Outline Table of contents 1.0 Introduction 1.1 General Description 2.0 Pin Descriptions 2.1 Pin Assignments 2.2 Pin Descriptions 2.3 Buffer Types 3.0 Functional Descriptions 3.1 IEEE 802.3 Alignment 3.2 Data Path Overview 3.2.1 Operating Modes 3.2.2 PTP 3.2.3 SerDEs 3.2.4 PCS25G 3.2.5 1G PCS 3.2.6 Cross Connect 3.2.7 1588 TSU 3.2.8 MAC 3.2.9 Flow Control Buffer 3.2.10 Loopbacks and Packet BIST 3.3 Frame Preemption Verify/Respond System Operation 3.4 Link Fault Signaling System Operation 3.5 Flow Control System Operation 3.5.1 Pause Handling and Flow Control 3.5.2 Basic Flow Control Handling 3.5.3 Advanced Flow Control Handling 3.6 Auto-negotiation and Training 3.6.1 25G Technology Ability 3.7 IEEE 1588 Operation 3.7.1 Implementation 3.7.2 1588 PLL 3.7.3 1588 LTC 3.7.4 Waveform Generator Output 3.7.5 Serial Timestamp Interface (STI) 3.7.6 Time Stamp Unit (TSU) 3.8 Clocking 3.8.1 Data Path Clocking 3.8.2 System Clock Generation 3.8.3 Synchronous Ethernet and Recovered Clocks 3.9 Device Management 3.9.1 SPI Client Interface 3.9.2 Management Data Input/Output (MDIO) Interface 3.10 Fiber Modules and Management 3.10.1 Two-Wire Interface 3.10.2 Fiber Module Support 3.11 LEDs 3.12 GPIOs 3.12.1 GPIO Interrupts 3.13 Resets and Power-On Self-Test 3.13.1 Resets 3.14 Host Interrupts 3.15 JTAG 3.15.1 Test TAP Controller 3.15.2 Test Modes 3.15.3 CSR Ring Access 3.15.4 Boundary Scan 3.16 Miscellaneous 3.16.1 Power Management 3.16.2 Warm ReSTART 3.16.3 Temperature Sensor 3.17 Configuration Straps 3.17.1 Function Mode Straps 4.0 Operational Characteristics 4.1 Absolute Maximum Ratings* 4.2 Operating Conditions** 4.3 Package Thermal Specifications 4.3.1 256-BGA 4.4 Power Consumption 4.4.1 Worst Case TWO Port Operation 4.4.2 Typical Usage TWO Port Operation 4.5 DC Specifications 4.5.1 SYSREFCK And LREFCK Clock Inputs DC Electrical Characteristics 4.5.2 SerDes DC Electrical Characteristics 4.6 AC Specifications 4.6.1 Power Sequencing 4.6.2 SYSREFCK And LREFCK Clock Inputs AC Electrical Characteristics 4.6.3 SerDes AC Electrical Characteristics 4.6.4 TWI Host Timing 4.6.5 MDC/MDIO Client 4.6.6 SPI Client 4.6.7 PPS and LSC Inputs/Outputs 4.6.8 Serial Timestamp Interface (STI) Format & Timing 4.6.9 Recovered Clock Timing Requirements 4.6.10 Reset Pin Configuration Strap Timing 4.6.11 JTAG Timing Values 5.0 Package Information 5.1 Top Marking 5.2 256-BGA Appendix A: Data Sheet Revision History Product Identification System The Microchip Web Site Customer Change Notification Service Customer Support