Datasheet LAN8023 (Microchip) - 4

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LAN8023 1.0 INTRODUCTION 1.1 General Description
The Microchip LAN8023 is a dual-port 1G/10G/25G serial optical Ethernet PHY transceiver which provides multiple line and host interface options. On the line interfaces, the supports transmission and reception of data over a variety of opti- cal module serial interfaces. These serial interfaces support both optical modules and copper cables. On the host inter- faces, the LAN8023 supports transmission and reception of data over a variety of chip-to-chip and backplane serial interfaces. An integrated Cross-Connect function enables any line port to connect to any host port. Host Redundancy options are provided. LAN8023 includes high-accuracy timestamping functions to support IEEE-1588 solutions using Microchip Ethernet switches, as wel as customer solutions based on SoCs and FPGAs. Synchronous Ethernet (SyncE) and TSN Frame Preemption is supported. The LAN8023 provides a complete suite of on-chip instrumentation including built-in self-test (BIST) functions, line-side and client-side circuit loopbacks, pat ern generation and error detection. It is wel -suited for SFP+ and SFP28 optical modules and direct-at ach copper (DAC) cabling as wel as chal enging backplane interface applications. An internal block diagram of the LAN8023 is shown in Figure 1-1.
FIGURE 1-1: LAN8023 INTERNAL BLOCK DIAGRAM t es ec s Host Host Host 1588 Line Line n Line n ce Port 0 SerDes PCS Engine PCS SerDes Port 0 rfac o fa e er ss-C o t Int Host Host Host Cr 1588 Line Line Line 2 e Int Port 1 SerDes PCS Engine PCS SerDes Port 1 n Hos 2x Li XC Failover Control 1588 PLL LEDs Straps and LTC GPIOs, LEDs, Module Management Reset Module Mgmt Interfaces Coma_Mode Temperature System PLL Interrupts GPIOs Monitor and clock gen MDIO Management JTAG Synchronization SPI Interfaces JTAG Ref CLKs 1PPS, TOD, Recovered Timestamps Clocks Out
The fol owing diagrams il ustrate three primary target use cases: • PHY with High-Accuracy 1588 Timestamping • PHY with Backplane Signal Reconditioning • PHY with Backplane Signal Reconditioning and System Redundancy DS00006161B-page 4  2025 Microchip Technology Inc. and its subsidiaries Document Outline Table of contents 1.0 Introduction 1.1 General Description 2.0 Pin Descriptions 2.1 Pin Assignments 2.2 Pin Descriptions 2.3 Buffer Types 3.0 Functional Descriptions 3.1 IEEE 802.3 Alignment 3.2 Data Path Overview 3.2.1 Operating Modes 3.2.2 PTP 3.2.3 SerDEs 3.2.4 PCS25G 3.2.5 1G PCS 3.2.6 Cross Connect 3.2.7 1588 TSU 3.2.8 MAC 3.2.9 Flow Control Buffer 3.2.10 Loopbacks and Packet BIST 3.3 Frame Preemption Verify/Respond System Operation 3.4 Link Fault Signaling System Operation 3.5 Flow Control System Operation 3.5.1 Pause Handling and Flow Control 3.5.2 Basic Flow Control Handling 3.5.3 Advanced Flow Control Handling 3.6 Auto-negotiation and Training 3.6.1 25G Technology Ability 3.7 IEEE 1588 Operation 3.7.1 Implementation 3.7.2 1588 PLL 3.7.3 1588 LTC 3.7.4 Waveform Generator Output 3.7.5 Serial Timestamp Interface (STI) 3.7.6 Time Stamp Unit (TSU) 3.8 Clocking 3.8.1 Data Path Clocking 3.8.2 System Clock Generation 3.8.3 Synchronous Ethernet and Recovered Clocks 3.9 Device Management 3.9.1 SPI Client Interface 3.9.2 Management Data Input/Output (MDIO) Interface 3.10 Fiber Modules and Management 3.10.1 Two-Wire Interface 3.10.2 Fiber Module Support 3.11 LEDs 3.12 GPIOs 3.12.1 GPIO Interrupts 3.13 Resets and Power-On Self-Test 3.13.1 Resets 3.14 Host Interrupts 3.15 JTAG 3.15.1 Test TAP Controller 3.15.2 Test Modes 3.15.3 CSR Ring Access 3.15.4 Boundary Scan 3.16 Miscellaneous 3.16.1 Power Management 3.16.2 Warm ReSTART 3.16.3 Temperature Sensor 3.17 Configuration Straps 3.17.1 Function Mode Straps 4.0 Operational Characteristics 4.1 Absolute Maximum Ratings* 4.2 Operating Conditions** 4.3 Package Thermal Specifications 4.3.1 256-BGA 4.4 Power Consumption 4.4.1 Worst Case TWO Port Operation 4.4.2 Typical Usage TWO Port Operation 4.5 DC Specifications 4.5.1 SYSREFCK And LREFCK Clock Inputs DC Electrical Characteristics 4.5.2 SerDes DC Electrical Characteristics 4.6 AC Specifications 4.6.1 Power Sequencing 4.6.2 SYSREFCK And LREFCK Clock Inputs AC Electrical Characteristics 4.6.3 SerDes AC Electrical Characteristics 4.6.4 TWI Host Timing 4.6.5 MDC/MDIO Client 4.6.6 SPI Client 4.6.7 PPS and LSC Inputs/Outputs 4.6.8 Serial Timestamp Interface (STI) Format & Timing 4.6.9 Recovered Clock Timing Requirements 4.6.10 Reset Pin Configuration Strap Timing 4.6.11 JTAG Timing Values 5.0 Package Information 5.1 Top Marking 5.2 256-BGA Appendix A: Data Sheet Revision History Product Identification System The Microchip Web Site Customer Change Notification Service Customer Support