Datasheet LAN8023 (Microchip) - 5

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LAN8023 FIGURE 1-2: PHY WITH HIGH-ACCURACY 1588 TIMESTAMPING
2x 1G/10G/25G SFP28 Socket ASIC/FPGA
LAN8023
SFP28 Socket Figure 1-2 details a printed circuit board (PCB) which includes an ASIC/FPGA, LAN8023, and SFP28 sockets. The LAN8023 may be required in such a design for the fol owing reasons: • Addition of advanced 1588 timestamping • Ethernet format conversion such as adding FEC or FEC termination / regeneration • Standardization on the LAN8023 for al such interfaces
FIGURE 1-3: PHY WITH BACKPLANE SIGNAL RECONDITIONING
2x 1G/10G/25G SFP28 Socket ASIC/FPGA ector ector ector ector
LAN8023
nn nn nn nn SFP28 Socket Co Co Co Co Figure 1-3 details a modular chassis system with the fol owing elements: • A pluggable switching or processing card containing an ASIC or FPGA with two serial interfaces to the backplane. Each interface is a separate 1G, 10G, or 25G Ethernet port. • A backplane integrated into the chassis, supporting a variety of pluggable cards. • A pluggable Optical Media Card with two SFP28 sockets. These sockets support pluggable optical modules such as 1 GbE SFP, 10 GbE SFP+, and 25 GbE SFP28. These sockets also support Direct Attach Copper (DAC) twi- nax cables. The signals are connected over the backplane using backplane Ethernet formats (1GBASE-KX, 10GBASE-KR, or 25GBASE-KR). The LAN8023 terminates the backplane signals, processes the Ethernet frames, and generates clean signals into the network, meeting optical module or cable specifications (and performs similar functions in the opposite direction). The LAN8023 can perform a range of processing functions in this role: • Signal reconditioning across the backplane, both electrical and timing • Ethernet format conversion functions between the backplane (host) and line interfaces, such as FEC termination / regeneration • Advanced 1588 timestamping
Note:
The LAN8023 only supports individual Ethernet ports up to 25 Gbps and does not support multi-lane Ethernet ports such as 40 Gbps or 100 Gbps.  2025 Microchip Technology Inc. and its subsidiaries DS00006161B-page 5 Document Outline Table of contents 1.0 Introduction 1.1 General Description 2.0 Pin Descriptions 2.1 Pin Assignments 2.2 Pin Descriptions 2.3 Buffer Types 3.0 Functional Descriptions 3.1 IEEE 802.3 Alignment 3.2 Data Path Overview 3.2.1 Operating Modes 3.2.2 PTP 3.2.3 SerDEs 3.2.4 PCS25G 3.2.5 1G PCS 3.2.6 Cross Connect 3.2.7 1588 TSU 3.2.8 MAC 3.2.9 Flow Control Buffer 3.2.10 Loopbacks and Packet BIST 3.3 Frame Preemption Verify/Respond System Operation 3.4 Link Fault Signaling System Operation 3.5 Flow Control System Operation 3.5.1 Pause Handling and Flow Control 3.5.2 Basic Flow Control Handling 3.5.3 Advanced Flow Control Handling 3.6 Auto-negotiation and Training 3.6.1 25G Technology Ability 3.7 IEEE 1588 Operation 3.7.1 Implementation 3.7.2 1588 PLL 3.7.3 1588 LTC 3.7.4 Waveform Generator Output 3.7.5 Serial Timestamp Interface (STI) 3.7.6 Time Stamp Unit (TSU) 3.8 Clocking 3.8.1 Data Path Clocking 3.8.2 System Clock Generation 3.8.3 Synchronous Ethernet and Recovered Clocks 3.9 Device Management 3.9.1 SPI Client Interface 3.9.2 Management Data Input/Output (MDIO) Interface 3.10 Fiber Modules and Management 3.10.1 Two-Wire Interface 3.10.2 Fiber Module Support 3.11 LEDs 3.12 GPIOs 3.12.1 GPIO Interrupts 3.13 Resets and Power-On Self-Test 3.13.1 Resets 3.14 Host Interrupts 3.15 JTAG 3.15.1 Test TAP Controller 3.15.2 Test Modes 3.15.3 CSR Ring Access 3.15.4 Boundary Scan 3.16 Miscellaneous 3.16.1 Power Management 3.16.2 Warm ReSTART 3.16.3 Temperature Sensor 3.17 Configuration Straps 3.17.1 Function Mode Straps 4.0 Operational Characteristics 4.1 Absolute Maximum Ratings* 4.2 Operating Conditions** 4.3 Package Thermal Specifications 4.3.1 256-BGA 4.4 Power Consumption 4.4.1 Worst Case TWO Port Operation 4.4.2 Typical Usage TWO Port Operation 4.5 DC Specifications 4.5.1 SYSREFCK And LREFCK Clock Inputs DC Electrical Characteristics 4.5.2 SerDes DC Electrical Characteristics 4.6 AC Specifications 4.6.1 Power Sequencing 4.6.2 SYSREFCK And LREFCK Clock Inputs AC Electrical Characteristics 4.6.3 SerDes AC Electrical Characteristics 4.6.4 TWI Host Timing 4.6.5 MDC/MDIO Client 4.6.6 SPI Client 4.6.7 PPS and LSC Inputs/Outputs 4.6.8 Serial Timestamp Interface (STI) Format & Timing 4.6.9 Recovered Clock Timing Requirements 4.6.10 Reset Pin Configuration Strap Timing 4.6.11 JTAG Timing Values 5.0 Package Information 5.1 Top Marking 5.2 256-BGA Appendix A: Data Sheet Revision History Product Identification System The Microchip Web Site Customer Change Notification Service Customer Support