Datasheet LAN8023 (Microchip) - 10

LAN8023 TABLE 2-3: PIN DESCRIPTIONS (CONTINUED) Name Symbol Buffer Type Description
Ethernet Line
TXOUT1N
AO Negative output signal of Port 1 dif erential pair. Port 1 Output
Note:
Internal 100 Ohms (nominal) dif erential Data Negative output termination.
Note:
External AC coupling is required and is typical y built into the SFP module. Ethernet Line
TXOUT1P
AO Positive output signal of Port 1 dif erential pair. Port 1 Output
Note:
Internal 100 Ohms (nominal) dif erential Data Positive output termination.
Note:
External AC coupling is required and is typical y built into the SFP module.
Ethernet (Host Interface)
Ethernet Host
TXIN0N
AI Negative input signal of Port 0 dif erential pair. Port 0 Input
Note:
Internal 100 Ohms (nominal) dif erential Data Negative input termination.
Note:
External AC coupling is required. Ethernet Host
TXIN0P
AI Positive input signal of Port 0 dif erential pair. Port 0 Input
Note:
Internal 100 Ohms (nominal) dif erential Data Positive input termination.
Note:
External AC coupling is required. Ethernet Host
TXIN1N
AI Negative input signal of Port 1 dif erential pair. Port 1 Input
Note:
Internal 100 Ohms (nominal) dif erential Data Negative input termination.
Note:
External AC coupling is required. Ethernet Host
TXIN1P
AI Positive input signal of Port 1 dif erential pair. Port 1 Input
Note:
Internal 100 Ohms (nominal) dif erential Data Positive input termination.
Note:
External AC coupling is required. Ethernet Host
RXOUT0N
AO Negative output signal of Port 0 dif erential pair. Port 0 Output
Note:
Internal 100 Ohms (nominal) dif erential Data Negative output termination.
Note:
External AC coupling is required. Ethernet Host
RXOUT0P
AO Positive output signal of Port 0 dif erential pair. Port 0 Output
Note:
Internal 100 Ohms (nominal) dif erential Data Positive input termination.
Note:
External AC coupling is required. Ethernet Host
RXOUT1N
AO Negative output signal of Port 1 dif erential pair. Port 1 Output
Note:
Internal 100 Ohms (nominal) dif erential Data Negative output termination.
Note:
External AC coupling is required. DS00006161B-page 10  2025 Microchip Technology Inc. and its subsidiaries Document Outline Table of contents 1.0 Introduction 1.1 General Description 2.0 Pin Descriptions 2.1 Pin Assignments 2.2 Pin Descriptions 2.3 Buffer Types 3.0 Functional Descriptions 3.1 IEEE 802.3 Alignment 3.2 Data Path Overview 3.2.1 Operating Modes 3.2.2 PTP 3.2.3 SerDEs 3.2.4 PCS25G 3.2.5 1G PCS 3.2.6 Cross Connect 3.2.7 1588 TSU 3.2.8 MAC 3.2.9 Flow Control Buffer 3.2.10 Loopbacks and Packet BIST 3.3 Frame Preemption Verify/Respond System Operation 3.4 Link Fault Signaling System Operation 3.5 Flow Control System Operation 3.5.1 Pause Handling and Flow Control 3.5.2 Basic Flow Control Handling 3.5.3 Advanced Flow Control Handling 3.6 Auto-negotiation and Training 3.6.1 25G Technology Ability 3.7 IEEE 1588 Operation 3.7.1 Implementation 3.7.2 1588 PLL 3.7.3 1588 LTC 3.7.4 Waveform Generator Output 3.7.5 Serial Timestamp Interface (STI) 3.7.6 Time Stamp Unit (TSU) 3.8 Clocking 3.8.1 Data Path Clocking 3.8.2 System Clock Generation 3.8.3 Synchronous Ethernet and Recovered Clocks 3.9 Device Management 3.9.1 SPI Client Interface 3.9.2 Management Data Input/Output (MDIO) Interface 3.10 Fiber Modules and Management 3.10.1 Two-Wire Interface 3.10.2 Fiber Module Support 3.11 LEDs 3.12 GPIOs 3.12.1 GPIO Interrupts 3.13 Resets and Power-On Self-Test 3.13.1 Resets 3.14 Host Interrupts 3.15 JTAG 3.15.1 Test TAP Controller 3.15.2 Test Modes 3.15.3 CSR Ring Access 3.15.4 Boundary Scan 3.16 Miscellaneous 3.16.1 Power Management 3.16.2 Warm ReSTART 3.16.3 Temperature Sensor 3.17 Configuration Straps 3.17.1 Function Mode Straps 4.0 Operational Characteristics 4.1 Absolute Maximum Ratings* 4.2 Operating Conditions** 4.3 Package Thermal Specifications 4.3.1 256-BGA 4.4 Power Consumption 4.4.1 Worst Case TWO Port Operation 4.4.2 Typical Usage TWO Port Operation 4.5 DC Specifications 4.5.1 SYSREFCK And LREFCK Clock Inputs DC Electrical Characteristics 4.5.2 SerDes DC Electrical Characteristics 4.6 AC Specifications 4.6.1 Power Sequencing 4.6.2 SYSREFCK And LREFCK Clock Inputs AC Electrical Characteristics 4.6.3 SerDes AC Electrical Characteristics 4.6.4 TWI Host Timing 4.6.5 MDC/MDIO Client 4.6.6 SPI Client 4.6.7 PPS and LSC Inputs/Outputs 4.6.8 Serial Timestamp Interface (STI) Format & Timing 4.6.9 Recovered Clock Timing Requirements 4.6.10 Reset Pin Configuration Strap Timing 4.6.11 JTAG Timing Values 5.0 Package Information 5.1 Top Marking 5.2 256-BGA Appendix A: Data Sheet Revision History Product Identification System The Microchip Web Site Customer Change Notification Service Customer Support