Datasheet LAN8023 (Microchip) - 8

LAN8023 TABLE 2-1: 256-BGA BALL ASSIGNMENTS (1-8) Bal 1 2 3 4 5 6 7 8 A VSS RXIN0N VDDHS_N TXOUT0P VDDHS_N RXIN1N VDDHS_N TXOUT1P B VSS RXIN0P VSS TXOUT0N VSS RXIN1P VSS TXOUT1N C GPIO32 GPIO33 FAILOVEROUT0/ RESET_N VSS VDDH18_N VDDH18_N VDDHS_N STRAP_RSVD_1 D LREFCKP LREFCKN FAILOVERIN0 JTAG_SEL COMA_MODE VSS VSS VDDHV_N E TEST TMS TDO TDI VDD VDD VDD VDD F TCK PTP1588_STI_CLK PTP1588_STI_DO PTP1588_STI VDD VDD VDD VDD _CS_N G PTP1588_LSC_2 PTP1588_LSC_1 PTP1588_LSC_0 RCKOUTB VDDO_A VSS VSS VSS H SPI_CLIENT SPI_CLIENT RCKOUTA MDIO VDDO_A VDDO_A VSS VSS _MISO _MOSI J SPI_CLIENT SPI_CLIENT MDC GPIO35 VDDO_A VDDO_A VSS VSS _SCK _SSN K VDDA VSSA GPIO34 TRST VDDO_18 VSS VSS VSS _1588APLL _1588APLL L PTP1588 PTP1588 PADDR4 PADDR3 VDDO_18 VDD VDD VDD _LSC_3_P _LSC_3_N M VDDA_SYSPLL VSSA_SYSPLL PADDR2 PADDR1 VDD VDD VDD VDD N SYSREFCKP SYSREFCKN PADDR0 RESERVED VDD VSS VSS VDDHV_S P VSS VSS RESERVED_L VDDO_A_MODE VDDO_B_MODE VDDH18_S VDDH18_S VDDHS_S R VSS RXOUT0N VSS TXIN0P VSS RXOUT1N VSS TXIN1P T VSS RXOUT0P VDDHS_S TXIN0N VDDHS_S RXOUT1P VDDHS_S TXIN1N TABLE 2-2: 256-BGA BALL ASSIGNMENTS (9-16) Bal 9 10 11 12 13 14 15 16 A VDDHS_N RESERVED VDDHS_N RESERVED VDDHS_N RESERVED VDDHS_N VSS B VSS RESERVED VSS RESERVED VSS RESERVED VSS RESERVED C VDDHS_N VDDH18_N VDDH18_N VSS VSS VSS VSS RESERVED D VDDHV_N VSS VSS VDD GPIO39 GPIO38 GPIO37 VSS E VDD VDD VDD VDD GPIO36 GPIO31 GPIO30 GPIO29 F VDD VDD VDD VDDO_B GPIO28 GPIO27 GPIO26 GPIO25 G VSS VSS VSS VDDO_B GPIO24 GPIO23 GPIO22 GPIO21 H VSS VSS VDDO_B VDDO_B GPIO20 GPIO19 GPIO18 GPIO17 J VSS VSS VDDO_B VDDO_B GPIO16 GPIO15 GPIO14 GPIO13 K VSS VSS VSS VDDO_18 GPIO12 GPIO11 GPIO10 GPIO9 L VDD VDD VDD RESERVED THERMD_Sn GPIO8 GPIO7 GPIO6 M VDD VDD VDD TESTA THERMD_Sp GPIO5 GPIO4 GPIO3 N VDDHV_S VSS VSS VDD THERMD_Fn GPIO2 GPIO1 GPIO0 P VDDHS_S VDDH18_S VDDH18_S VSS THERMD_Fp VSS VSS RESERVED R VSS RESERVED VSS RESERVED VSS RESERVED VSS RESERVED T VDDHS_S RESERVED VDDHS_S RESERVED VDDHS_S RESERVED VDDHS_S VSS
DS00006161B-page 8  2025 Microchip Technology Inc. and its subsidiaries Document Outline Table of contents 1.0 Introduction 1.1 General Description 2.0 Pin Descriptions 2.1 Pin Assignments 2.2 Pin Descriptions 2.3 Buffer Types 3.0 Functional Descriptions 3.1 IEEE 802.3 Alignment 3.2 Data Path Overview 3.2.1 Operating Modes 3.2.2 PTP 3.2.3 SerDEs 3.2.4 PCS25G 3.2.5 1G PCS 3.2.6 Cross Connect 3.2.7 1588 TSU 3.2.8 MAC 3.2.9 Flow Control Buffer 3.2.10 Loopbacks and Packet BIST 3.3 Frame Preemption Verify/Respond System Operation 3.4 Link Fault Signaling System Operation 3.5 Flow Control System Operation 3.5.1 Pause Handling and Flow Control 3.5.2 Basic Flow Control Handling 3.5.3 Advanced Flow Control Handling 3.6 Auto-negotiation and Training 3.6.1 25G Technology Ability 3.7 IEEE 1588 Operation 3.7.1 Implementation 3.7.2 1588 PLL 3.7.3 1588 LTC 3.7.4 Waveform Generator Output 3.7.5 Serial Timestamp Interface (STI) 3.7.6 Time Stamp Unit (TSU) 3.8 Clocking 3.8.1 Data Path Clocking 3.8.2 System Clock Generation 3.8.3 Synchronous Ethernet and Recovered Clocks 3.9 Device Management 3.9.1 SPI Client Interface 3.9.2 Management Data Input/Output (MDIO) Interface 3.10 Fiber Modules and Management 3.10.1 Two-Wire Interface 3.10.2 Fiber Module Support 3.11 LEDs 3.12 GPIOs 3.12.1 GPIO Interrupts 3.13 Resets and Power-On Self-Test 3.13.1 Resets 3.14 Host Interrupts 3.15 JTAG 3.15.1 Test TAP Controller 3.15.2 Test Modes 3.15.3 CSR Ring Access 3.15.4 Boundary Scan 3.16 Miscellaneous 3.16.1 Power Management 3.16.2 Warm ReSTART 3.16.3 Temperature Sensor 3.17 Configuration Straps 3.17.1 Function Mode Straps 4.0 Operational Characteristics 4.1 Absolute Maximum Ratings* 4.2 Operating Conditions** 4.3 Package Thermal Specifications 4.3.1 256-BGA 4.4 Power Consumption 4.4.1 Worst Case TWO Port Operation 4.4.2 Typical Usage TWO Port Operation 4.5 DC Specifications 4.5.1 SYSREFCK And LREFCK Clock Inputs DC Electrical Characteristics 4.5.2 SerDes DC Electrical Characteristics 4.6 AC Specifications 4.6.1 Power Sequencing 4.6.2 SYSREFCK And LREFCK Clock Inputs AC Electrical Characteristics 4.6.3 SerDes AC Electrical Characteristics 4.6.4 TWI Host Timing 4.6.5 MDC/MDIO Client 4.6.6 SPI Client 4.6.7 PPS and LSC Inputs/Outputs 4.6.8 Serial Timestamp Interface (STI) Format & Timing 4.6.9 Recovered Clock Timing Requirements 4.6.10 Reset Pin Configuration Strap Timing 4.6.11 JTAG Timing Values 5.0 Package Information 5.1 Top Marking 5.2 256-BGA Appendix A: Data Sheet Revision History Product Identification System The Microchip Web Site Customer Change Notification Service Customer Support