Datasheet HIP2210, HIP2211 (Renesas) - 10

link to page 11 link to page 11 link to page 11 link to page 11 link to page 11 link to page 11 link to page 11 HIP2210, HIP2211 2. Specifications VDD = HB = 12V; VSS = HS = 0V; HI = LI = 0V to 5V; PWM = 0V to VREF; RDT = 1kΩ, 10kΩ, or 100kΩ. No load on LO or HO, unless otherwise specified.
Boldface limits apply across the operating temperature range, - 40°C to +125°C. (Continued) Min Max Parameters Symbol Test Conditions (Note 11) Typ (Note 11) Units
HO Turn-Off Propagation Delay tPDHI_F HI = 1 to 0; HB - HS = 12V - 15
30
ns HI = 1 to 0; HB - HS = 6V - 15
30
ns HO Turn-On Propagation Delay tPDHI_R HI = 0 to 1; HB - HS = 12V - 15
30
ns HI = 0 to 1; HB - HS = 6V - 15
30
ns Propagation Delay Matching tMATCH_LH LI = 1 to 0; HI = 0 to 1
-6
1.5
6
ns LO falling to HO rising tMATCH_HL HI = 1 to 0; LI = 0 to 1
-6
1.5
6
ns HO falling to LO rising
Propagation Delays (HIP2210)
HO Turn-Off Propagation Delay tPDHO PWM falling to HO falling; - 30
40
ns VREF = 5V; RDT = 1kΩ; VDD = HB - HS = 12V PWM falling to HO falling; - 30
40
ns VREF = 5V; RDT = 1kΩ; VDD = HB - HS = 6V LO Turn-Off Propagation Delay tPDLO PWM rising to LO falling; - 30
43
ns VREF = 5V; RDT = 1kΩ; VDD = HB - HS = 12V PWM rising to LO falling; - 30
43
ns VREF = 5V; RDT = 1kΩ; VDD = HB - HS = 6V Turn-Off Propagation Delay Matching tPDMATCH tPDHO - tPDLO; -10 2
10
ns VREF = 5V; RDT = 1kΩ; VDD = HB - HS = 12V tPDHO - tPDLO; -10 2
10
ns VREF = 5V; RDT = 1kΩ; VDD = HB - HS = 6V PWM High to Mid State to HO Off tPD_PWM_HM VREF = 5V; RDT = 1kΩ; - 70
90
ns Propagation Delay PWM Mid to High State to HO On tPD_PWM_MH VREF = 5V; RDT = 1kΩ; - 60
82
ns Propagation Delay PWM Low to Mid state to LO Off Propagation tPD_PWM_LM VREF

PWM 5V to 2.5V PWM 2.5V to 5V = 5V; RDT = 1kΩ; - 70
87
ns Delay PWM 0V to 2.5V PWM Mid to Low State to LO On Propagation tPD_PWM_ML VREF = 5V; RDT = 1kΩ; - 60
79
ns Delay PWM 2.5V to 0V
RDT Programmable Dead Time Delays (HIP2210)
Minimum Dead Time Delay (Note 12) tDTHL_MIN RDT = 1kΩ,
5
11
18
ns HO Falling to LO Rising PWM high to low Minimum Dead Time Delay (Note 12) tDTLH_MIN RDT = 1kΩ,
5
11
18
ns LO Falling to HO Rising PWM low to high Low Range Delay (Note 12) tDTHL_LOW RDT = 10kΩ,
30
36
45
ns HO Falling to LO Rising PWM high to low Low Range Delay (Note 12) tDTLH_LOW RDT = 10kΩ,
30
36
45
ns LO Falling to HO Rising PWM low to high High Range Delay (Note 12) tDTHL_HIGH RDT = 100kΩ,
300
360
425
ns HO Falling to LO Rising PWM high to low High Range Delay (Note 12) tDTLH_HIGH RDT = 100kΩ,
300
360
425
ns LO Falling to HO Rising PWM low to high Maximum Dead Time Delay (Note 12) tDTHL_MAX RDT = 200kΩ, - 715 - ns HO Falling to LO Rising PWM high to low FN9347 Rev.1.01 Page 10 of 27 Jun.23.20 Document Outline Related Literature Features Applications Contents 1. Overview 1.1 Block Diagrams 1.2 Ordering Information 1.3 Pin Configurations 1.4 Pin Descriptions 2. Specifications 2.1 Absolute Maximum Ratings 2.2 Thermal Information 2.3 Recommended Operating Conditions 2.4 Electrical Specifications 2.5 Switching Specifications 2.6 Timing Diagrams 3. Typical Performance Curves 4. Functional Description 4.1 Gate Drive for NMOS Half-Bridge 4.2 Functional Overview 5. Applications Information 5.1 HI/LI Input Control (HIP2211 Only) 5.2 PWM Input Control (HIP2210 Only) 5.3 VREF Input (HIP2210 Only) 5.4 EN Pin (HIP2210 Only) 5.5 Power Sequencing HIP2210 5.6 Selecting the Boot Capacitor Value 5.7 VDD Decoupling Capacitor 5.8 RDT and Dead Time Delay (HIP2210 Only) 5.9 HO and LO Outputs 5.10 Power Dissipation 5.10.1 Gate Power (for the HO and LO Outputs) 5.10.2 Boot Diode Dissipation 5.10.3 Dynamic Operating Current 5.10.4 Total Power Dissipation 5.10.5 Junction Operating Temperature 6. PCB Layout Guidelines 6.1 PCB Layout and EPAD Recommendation 7. Revision History 8. Package Outline Drawings