Datasheet HIP2210, HIP2211 (Renesas) - 9

link to page 11 link to page 11 HIP2210, HIP2211 2. Specifications VDD = HB = EN = 12V; VSS = HS = 0V; HI = LI = 0; VREF = 5V; PWM = 2.5V. No load on LO or HO, unless otherwise specified.
Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued) Min Max Parameters Symbol Test Conditions (Note 11) Typ (Note 11) Units
VDD Rising UVLO Delay Characterization only. No limits. - 1 - µs VDD Falling UVLO Delay Characterization only. No limits. - 2 - µs VHB Rising Threshold VHBR
4.8
5.1
5.4
V VHB Falling Threshold VHBF
4.25
4.6
4.85
V VHB Threshold Hysteresis VHBH - 0.5 - V VHB Rising UVLO Delay Characterization only. No limits. - 10 - µs VHB Falling UVLO Delay Characterization only. No limits. - 12 - µs
Bootstrap Diode
Low Current Forward Voltage VFL IVDD - HB = 100µA - 0.65
0.85
V High Current Forward Voltage VFH IVDD - HB = 100mA - 0.85
1
V Dynamic Resistance RD RD = ΔVD/ΔIVDD-HB - 0.5
0.9
Ω IVDD-HB = 80mA and 100mA Reverse Bias Leakage IR VHB = VHS = 100V; VDD = 0V - 0.11 - µA Reverse Recovery Time tRR 100mA forward to 100V reverse - 50 - ns
LO Gate Driver
Low-Level Output Voltage VOL_LO ILO = 100mA sink - 0.1
0.17
V High-Level Output Voltage VOH_LO ILO = 100mA source - 0.16
0.27
V VOH_LO = VDD - VLO Peak Pull-Up Source Current IOH_LO VLO = 0V; Limits are internal - 3 - A specifications only Peak Pull-Down Sink Current IOL_LO VLO = 12V; Limits are internal - 4 - A specifications only LO Pin Pull-Down Resistance RLO VDD = 0V; LO = 100mV; To VSS - 140 - kΩ
HO Gate Driver
Low-Level Output Voltage VOL_HO IHO = 100mA sink Peak Pull-Up Current IOH_HO VHO = 0V; Limits ar

- 0.1
0.17
V High-Level Output Voltage VOH_HO IHO = 100mA source - 0.16
0.27
V VOH_HO = VHB - VHO e internal - 3 - A specifications only. Peak Pull-Down Current IOL_HO VHO = VHB; Limits are internal - 4 - A specifications only. HO Pin Pull-Down Resistance RHO HB - HS = 0V; HO = 100mV; To HS - 450 - kΩ
2.5 Switching Specifications
VDD = HB = 12V; VSS = HS = 0V; HI = LI = 0V to 5V; PWM = 0V to VREF; RDT = 1kΩ, 10kΩ, or 100kΩ. No load on LO or HO, unless otherwise specified.
Boldface limits apply across the operating temperature range, - 40°C to +125°C. Min Max Parameters Symbol Test Conditions (Note 11) Typ (Note 11) Units Propagation Delays (HIP2211)
LO Turn-Off Propagation Delay tPDLI_F LI = 1 to 0; VDD = 12V - 15
30
ns LI = 1 to 0; VDD = 6V - 15
30
ns LO Turn-On Propagation Delay tPDLI_R LI = 0 to 1; VDD = 12V - 15
30
ns LI = 0 to 1; VDD = 6V - 15
30
ns FN9347 Rev.1.01 Page 9 of 27 Jun.23.20 Document Outline Related Literature Features Applications Contents 1. Overview 1.1 Block Diagrams 1.2 Ordering Information 1.3 Pin Configurations 1.4 Pin Descriptions 2. Specifications 2.1 Absolute Maximum Ratings 2.2 Thermal Information 2.3 Recommended Operating Conditions 2.4 Electrical Specifications 2.5 Switching Specifications 2.6 Timing Diagrams 3. Typical Performance Curves 4. Functional Description 4.1 Gate Drive for NMOS Half-Bridge 4.2 Functional Overview 5. Applications Information 5.1 HI/LI Input Control (HIP2211 Only) 5.2 PWM Input Control (HIP2210 Only) 5.3 VREF Input (HIP2210 Only) 5.4 EN Pin (HIP2210 Only) 5.5 Power Sequencing HIP2210 5.6 Selecting the Boot Capacitor Value 5.7 VDD Decoupling Capacitor 5.8 RDT and Dead Time Delay (HIP2210 Only) 5.9 HO and LO Outputs 5.10 Power Dissipation 5.10.1 Gate Power (for the HO and LO Outputs) 5.10.2 Boot Diode Dissipation 5.10.3 Dynamic Operating Current 5.10.4 Total Power Dissipation 5.10.5 Junction Operating Temperature 6. PCB Layout Guidelines 6.1 PCB Layout and EPAD Recommendation 7. Revision History 8. Package Outline Drawings