Datasheet IP101G (IC Plus) - 7

IP101G Data Sheet
Features comparison between IP101G and IP101A/IP101AH
Table 1 Features comparison between IP101G and IP101A/IP101AH Product Name IP101GR IP101G IP101GA IP101A IP101AH Package Type 32pin QFN Dice 48pin LQFP 48pin LQFP REGOUT(1) Output Voltage 1.0V, pin28 1.0V, pad5 1.0V, pin8 2.5V, pin32 and location and pad11 REGIN Input Voltage and NA(2) 1.0V, pad23 NA 2.5V, pin8 location and pad26 RMII mode setting Pin4 Pad18 Pin1 Pin1 and pin44 Fiber mode setting: Pin19 Pad39 Pin22 NA Pin24 and pin48 Fiber FXSD signal: Pin1 Pad13 Pin43 Pin37 Number of LED 2 4 4 5 LED mode 1 and 2 1 and 2 LED Blink Timing On 26ms -> Off 78ms On 26ms -> Off 78ms PHY address number(3) Single: 0 ~ 1 Single: 0 ~ 7 Single: 0 ~ 31 Multi: 2 ~ 31 Multi: 8 ~ 31 Center-tap of transformer Do not connect to any power 2.5V input power Built-in 49.9ohm resistors Yes No Power consumption ~150mW ~480mW Process 85nm 0.25μm IEEE 802.3az Yes No 10Base TX amplitude ~1.75V (10Base-Te) ~2.5V (10Base-T) WOL+ (Wake On LAN Plus) Yes No Analog OFF Yes No 16 bit RX counter Yes No 9 bit RXER/CRC counter Yes No RX to TX Loopback Yes No Loopback MII/RMII Yes Yes SNI mode No Yes Note 1: Regulator voltage output is for internal use only. Do not supply to any other device. Note 2: Not available for this function. The 1.0V is supplied by the regulator that built-in the chip. Note 3: Do not let these PHY address pins floating for the latched-in settings after the power is ready. 7/66 May 20, 2014 Copyright © 2011, IC Plus Corp. IP101G-DS-R01 Document Outline Features comparison between IP101G and IP101A/IP101AH 1 Pin diagram 2 Dice pad information 3 Pin description 3.1 IP101GA pin description 3.2 IP101GR/GRI pin description 4 Register Descriptions 4.1 Register Page mode Control Register 4.2 MII Registers 4.3 MMD Control Register 4.4 MMD Data Register 4.5 RX Counter Register 4.6 LED Pin Control Register 4.7 WOL+ Control Register 4.8 UTP PHY Specific Control Register 4.9 Digital IO Pin Control Register 5 Function Description 5.1 Major Functional Block Description 5.1.1 Transmission Description 5.1.2 MII and Management Control Interface 5.1.3 RMII Interface 5.1.4 Flexible Clock Source 5.1.5 Auto-Negotiation and Related Information 5.1.6 Auto-MDIX function 5.2 PHY Address Configuration 5.3 Power Management Tool 5.3.1 Auto Power Saving Mode 5.3.2 IEEE802.3az EEE (Energy Efficient Ethernet) 5.3.3 Force power down 5.3.4 WOL+ operation mode 5.4 LED Mode Configuration 5.5 LED Blink Timing 5.6 Repeater Mode 5.7 Interrupt 5.8 Miscellaneous 5.9 Serial Management Interface 5.10 Fiber Mode Setting 5.11 Jumbo Frame 6 Layout Guideline 6.1 General Layout Guideline 6.2 Twisted Pair recommendation 7 Electrical Characteristics 7.1 Absolute Maximum Rating 7.2 DC Characteristics 7.3 Crystal Specifications 7.4 AC Timing 7.4.1 Reset, Pin Latched-in, Clock and Power Source 7.4.2 MII Timing 7.4.3 RMII Timing 7.4.4 SMI Timing 7.4.5 MDI to MII latency delay time 7.5 Thermal Data 8 Order Information 9 Physical Dimensions 9.1 48-PIN LQFP 9.2 32-PIN QFN