Datasheet IP101G (IC Plus) - 6

IP101G Data Sheet
Revision History Revision # Change Description
IP101G-DS-R01 Initial release. IP101G-DS-R01-20120808 1) Correct the I/O type of IP101GA pin description to O(Ouput) for pin24 RXER. 2) Change the pin name from DVDD33_IO to VDDIO. IP101G-DS-R01-20120821 1) Change the default value of register P16R27 from 0x0022 to 0x0012. 2) Remove I/O Slew Rate Control Register. 3) Change the register location RMII_WITH_ER from P16R29[0] to P16R29[7]. IP101G-DS-R01-20120927 1) Add more description of low power idle (LPI) state in MII and RMII modes. 2) Correct the typo of Physical Dimensions. IP101G-DS-R01-20121101 Change the LED blink timing from “On 80ms -> Off (20~40)ms” to “On 26ms -> Off 78ms”. IP101G-DS-R01-20121113 Add more function description to support Jumbo Frame. IP101G-DS-R01-20121127 Change the LED mode function as same as IP101A. IP101G-DS-R01-20121224 Add the notice that does not let these PHY address pins floating for the latched-in settings after the power is ready. IP101G-DS-R01-20130206 Change the AC timing Tclk_MII_rdy in Table 14 from 10ms Min. to 10ms Max. IP101G-DS-R01-20130312 1) Add more Min. and Max value on the AC Timing table. 2) Add thermal data on the Table 20. IP101G-DS-R01-20130507 Add LED Pin Driving Control Register. IP101G-DS-R01-20130621 Add IP101GRI 2.5V I/O power supply. IP101G-DS-R01-20130712 Modify WOL+ programming guide. IP101G-DS-R01-20130830 Modify Magic packet MAC_Address description. IP101G-DS-R01-20130905 Modify LED Control Register. IP101G-DS-R01-20130927 Modify MDC clock period can be to 300ns. IP101G-DS-R01-20131110 Add the symbol "Bottom view" and "Top view" in Physical Dimensions. IP101G-DS-R01-20131115 Add Equivalent Series Resistance and Drive Level in Crystal Specifications. IP101G-DS-R01-20140114 1) Make more clear between 100Mbps (25M nibbles/s) and 25M code-groups/s in Figure 1 Flow chart of IP101G. 2) Change all symbols from “VQFN” to “QFN”. 3) Add the key word “Fiber” in Table 11 I/O Electrical Characteristics. 4) Add register PHY_ADDRESS in Page16 Reg29 bit[12:8]. 5) Add Table 20 MDI to MII latency delay time. 6) Add table 5 PHY Address Configuration by register description IP101G-DS-R01-20140224 Modify Register4 Next Page bit symbol “RO” to “RW”. IP101G-DS-R01-20140328 Delete termination resistors description of Layout Guideline 6.2. IP101G-DS-R01-20140520 1) Modify UTP PHY Interrupt control/status Register description. 2) Add special Reset request description.
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6/66 May 20, 2014 Copyright © 2011, IC Plus Corp. IP101G-DS-R01 Document Outline Features comparison between IP101G and IP101A/IP101AH 1 Pin diagram 2 Dice pad information 3 Pin description 3.1 IP101GA pin description 3.2 IP101GR/GRI pin description 4 Register Descriptions 4.1 Register Page mode Control Register 4.2 MII Registers 4.3 MMD Control Register 4.4 MMD Data Register 4.5 RX Counter Register 4.6 LED Pin Control Register 4.7 WOL+ Control Register 4.8 UTP PHY Specific Control Register 4.9 Digital IO Pin Control Register 5 Function Description 5.1 Major Functional Block Description 5.1.1 Transmission Description 5.1.2 MII and Management Control Interface 5.1.3 RMII Interface 5.1.4 Flexible Clock Source 5.1.5 Auto-Negotiation and Related Information 5.1.6 Auto-MDIX function 5.2 PHY Address Configuration 5.3 Power Management Tool 5.3.1 Auto Power Saving Mode 5.3.2 IEEE802.3az EEE (Energy Efficient Ethernet) 5.3.3 Force power down 5.3.4 WOL+ operation mode 5.4 LED Mode Configuration 5.5 LED Blink Timing 5.6 Repeater Mode 5.7 Interrupt 5.8 Miscellaneous 5.9 Serial Management Interface 5.10 Fiber Mode Setting 5.11 Jumbo Frame 6 Layout Guideline 6.1 General Layout Guideline 6.2 Twisted Pair recommendation 7 Electrical Characteristics 7.1 Absolute Maximum Rating 7.2 DC Characteristics 7.3 Crystal Specifications 7.4 AC Timing 7.4.1 Reset, Pin Latched-in, Clock and Power Source 7.4.2 MII Timing 7.4.3 RMII Timing 7.4.4 SMI Timing 7.4.5 MDI to MII latency delay time 7.5 Thermal Data 8 Order Information 9 Physical Dimensions 9.1 48-PIN LQFP 9.2 32-PIN QFN