Datasheet TDA8920CTH (NXP) - 6

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NXP Semiconductors TDA8920C 2
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110 W class-D power amplifier
The TDA8920C single-chip class-D amplifier contains high-power switches, drivers, timing and handshaking between the power switches, along with some control logic. To ensure maximum system robustness, an advanced protection strategy has been implemented to provide overvoltage, overtemperature and overcurrent protection. Each of the two audio channels contains a PWM modulator, an analog feedback loop and a differential input stage. The TDA8920C also contains circuits common to both channels such as the oscillator, all reference sources, the mode interface and a digital timing manager. The two independent amplifier channels feature high output power, high efficiency, low distortion and low quiescent currents, and can be connected in the following configurations:
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Stereo Single-Ended (SE)
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Mono Bridge-Tied Load (BTL) The amplifier system can be switched to one of three operating modes using pin MODE:
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Standby mode: featuring very low quiescent current
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Mute mode: the amplifier is operational but the audio signal at the output is suppressed by disabling the voltage-to-current (VI) converter input stages
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Operating mode: the amplifier is fully operational, de-muted and can deliver an output signal A slowly rising voltage should be applied (e.g. via an RC network) to pin MODE to ensure pop noise-free start-up. The bias-current setting of the (VI converter) input stages is related to the voltage on the MODE pin. In Mute mode, the bias-current setting of the VI converters is zero (VI converters are disabled). In Operating mode, the bias current is at a maximum. The time constant required to apply the DC output offset voltage gradually between Mute and Operating mode levels can be generated using an RC network connected to pin MODE. An example of a switching circuit for driving pin MODE is illustrated in Figure 4. If the capacitor was omitted, the very short switching time constant could result in audible pop noises being generated at start-up (depending on the DC output offset voltage and loudspeaker used). +5 V 5.6 kΩ 470 Ω mode control 5.6 kΩ 10 µF mute/ standby/ S1 S2 operating operating SGND 010aaa552
Fig 4. Example of mode selection circuit
TDA8920C_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 6 of 39
Document Outline 1. General description 2. Features 3. Applications 4. Quick reference data 5. Ordering information 6. Block diagram 7. Pinning information 7.1 Pinning 7.2 Pin description 8. Functional description 8.1 General 8.2 Pulse-width modulation frequency 8.3 Protection 8.3.1 Thermal protection 8.3.1.1 Thermal FoldBack (TFB) 8.3.1.2 OverTemperature Protection (OTP) 8.3.2 OverCurrent Protection (OCP) 8.3.3 Window Protection (WP) 8.3.4 Supply voltage protection 8.4 Differential audio inputs 9. Limiting values 10. Thermal characteristics 11. Static characteristics 12. Dynamic characteristics 12.1 Switching characteristics 12.2 Stereo SE configuration characteristics 12.3 Mono BTL application characteristics 13. Application information 13.1 Mono BTL application 13.2 Pin MODE 13.3 Estimating the output power 13.3.1 Single-Ended (SE) 13.3.2 Bridge-Tied Load (BTL) 13.4 External clock 13.5 Heatsink requirements 13.6 Pumping effects 13.7 Application schematic 13.8 Curves measured in reference design 14. Package outline 15. Soldering of SMD packages 15.1 Introduction to soldering 15.2 Wave and reflow soldering 15.3 Wave soldering 15.4 Reflow soldering 16. Soldering of through-hole mount packages 16.1 Introduction to soldering through-hole mount packages 16.2 Soldering by dipping or by solder wave 16.3 Manual soldering 16.4 Package related soldering information 17. Revision history 18. Legal information 18.1 Data sheet status 18.2 Definitions 18.3 Disclaimers 18.4 Trademarks 19. Contact information 20. Contents