Datasheet TDA8920CTH (NXP) - 7
| 制造商 | NXP |
| 描述 | 2 x 110 W Class-D Power Amplifier |
| 页数 / 页 | 39 / 7 — NXP Semiconductors. TDA8920C. 110 W class-D power amplifier. Upper … |
| 文件格式/大小 | PDF / 237 Kb |
| 文件语言 | 英语 |
NXP Semiconductors. TDA8920C. 110 W class-D power amplifier. Upper diagram:. Lower diagram:. Fig 5
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NXP Semiconductors TDA8920C 2
×
110 W class-D power amplifier
To ensure the coupling capacitors at the inputs (CIN in Figure 10) are fully charged before the outputs start switching, a delay is inserted during the transition from Mute to Operating mode. An overview of the start-up timing is provided in Figure 5. For proper switch-off, the MODE pin should be forced LOW at least 100 ms before the supply lines (VDDA and VSSA) drop below 12.5 V. audio output (1) modulated PWM VMODE 50 % duty cycle operating > 4.2 V mute 2.2 V < VMODE < 3 V standby 0 V (SGND) time 100 ms > 350 ms 50 ms audio output (1) modulated PWM VMODE 50 % duty cycle operating > 4.2 V mute 2.2 V < VMODE < 3 V standby 0 V (SGND) time 100 ms > 350 ms 50 ms 001aah657 (1) First 1⁄4 pulse down.
Upper diagram:
When switching from Standby to Mute, there is a delay of approximately 100 ms before the output starts switching. The audio signal will become available once VMODE reaches the Operating mode level (see Table 8), but not earlier than 150 ms after switching to Mute. To start-up pop noise-free, it is recommended that the time constant applied to pin MODE be at least 350 ms for the transition between Mute and Operating modes.
Lower diagram:
When switching directly from Standby to Operating mode, there is a delay of 100 ms before the outputs start switching. The audio signal becomes available after a second delay of 50 ms. To start-up pop noise-free, it is recommended that the time-constant applied to pin MODE be at least 500 ms for the transition between Standby and Operating modes.
Fig 5. Timing on mode selection input pin MODE
TDA8920C_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 7 of 39
Document Outline 1. General description 2. Features 3. Applications 4. Quick reference data 5. Ordering information 6. Block diagram 7. Pinning information 7.1 Pinning 7.2 Pin description 8. Functional description 8.1 General 8.2 Pulse-width modulation frequency 8.3 Protection 8.3.1 Thermal protection 8.3.1.1 Thermal FoldBack (TFB) 8.3.1.2 OverTemperature Protection (OTP) 8.3.2 OverCurrent Protection (OCP) 8.3.3 Window Protection (WP) 8.3.4 Supply voltage protection 8.4 Differential audio inputs 9. Limiting values 10. Thermal characteristics 11. Static characteristics 12. Dynamic characteristics 12.1 Switching characteristics 12.2 Stereo SE configuration characteristics 12.3 Mono BTL application characteristics 13. Application information 13.1 Mono BTL application 13.2 Pin MODE 13.3 Estimating the output power 13.3.1 Single-Ended (SE) 13.3.2 Bridge-Tied Load (BTL) 13.4 External clock 13.5 Heatsink requirements 13.6 Pumping effects 13.7 Application schematic 13.8 Curves measured in reference design 14. Package outline 15. Soldering of SMD packages 15.1 Introduction to soldering 15.2 Wave and reflow soldering 15.3 Wave soldering 15.4 Reflow soldering 16. Soldering of through-hole mount packages 16.1 Introduction to soldering through-hole mount packages 16.2 Soldering by dipping or by solder wave 16.3 Manual soldering 16.4 Package related soldering information 17. Revision history 18. Legal information 18.1 Data sheet status 18.2 Definitions 18.3 Disclaimers 18.4 Trademarks 19. Contact information 20. Contents
NXP Semiconductors TDA8920C 2
×
110 W class-D power amplifier
To ensure the coupling capacitors at the inputs (CIN in Figure 10) are fully charged before the outputs start switching, a delay is inserted during the transition from Mute to Operating mode. An overview of the start-up timing is provided in Figure 5. For proper switch-off, the MODE pin should be forced LOW at least 100 ms before the supply lines (VDDA and VSSA) drop below 12.5 V. audio output (1) modulated PWM VMODE 50 % duty cycle operating > 4.2 V mute 2.2 V < VMODE < 3 V standby 0 V (SGND) time 100 ms > 350 ms 50 ms audio output (1) modulated PWM VMODE 50 % duty cycle operating > 4.2 V mute 2.2 V < VMODE < 3 V standby 0 V (SGND) time 100 ms > 350 ms 50 ms 001aah657 (1) First 1⁄4 pulse down.
Upper diagram:
When switching from Standby to Mute, there is a delay of approximately 100 ms before the output starts switching. The audio signal will become available once VMODE reaches the Operating mode level (see Table 8), but not earlier than 150 ms after switching to Mute. To start-up pop noise-free, it is recommended that the time constant applied to pin MODE be at least 350 ms for the transition between Mute and Operating modes.
Lower diagram:
When switching directly from Standby to Operating mode, there is a delay of 100 ms before the outputs start switching. The audio signal becomes available after a second delay of 50 ms. To start-up pop noise-free, it is recommended that the time-constant applied to pin MODE be at least 500 ms for the transition between Standby and Operating modes.
Fig 5. Timing on mode selection input pin MODE
TDA8920C_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 7 of 39
Document Outline 1. General description 2. Features 3. Applications 4. Quick reference data 5. Ordering information 6. Block diagram 7. Pinning information 7.1 Pinning 7.2 Pin description 8. Functional description 8.1 General 8.2 Pulse-width modulation frequency 8.3 Protection 8.3.1 Thermal protection 8.3.1.1 Thermal FoldBack (TFB) 8.3.1.2 OverTemperature Protection (OTP) 8.3.2 OverCurrent Protection (OCP) 8.3.3 Window Protection (WP) 8.3.4 Supply voltage protection 8.4 Differential audio inputs 9. Limiting values 10. Thermal characteristics 11. Static characteristics 12. Dynamic characteristics 12.1 Switching characteristics 12.2 Stereo SE configuration characteristics 12.3 Mono BTL application characteristics 13. Application information 13.1 Mono BTL application 13.2 Pin MODE 13.3 Estimating the output power 13.3.1 Single-Ended (SE) 13.3.2 Bridge-Tied Load (BTL) 13.4 External clock 13.5 Heatsink requirements 13.6 Pumping effects 13.7 Application schematic 13.8 Curves measured in reference design 14. Package outline 15. Soldering of SMD packages 15.1 Introduction to soldering 15.2 Wave and reflow soldering 15.3 Wave soldering 15.4 Reflow soldering 16. Soldering of through-hole mount packages 16.1 Introduction to soldering through-hole mount packages 16.2 Soldering by dipping or by solder wave 16.3 Manual soldering 16.4 Package related soldering information 17. Revision history 18. Legal information 18.1 Data sheet status 18.2 Definitions 18.3 Disclaimers 18.4 Trademarks 19. Contact information 20. Contents