Datasheet LMC555 (Texas Instruments) - 3

LMC555 www.ti.com
SNAS558M – FEBRUARY 2000 – REVISED JULY 2016
5 Pin Configuration and Functions D, DGK, and P Packages 8-Pin SOIC, VSSOP, and PDIP YPB Package (Top View) 8-Pin DSBGA (Top View) Pin Functions PIN I/O DESCRIPTION SOIC, VSSOP, and DSBGA NO. NAME PDIP NO.
1 A3 GND O Ground reference voltage 2 B3 Trigger I Responsible for transition of the flip-flop from set to reset. The output of the timer depends on the amplitude of the external trigger pulse applied to this pin 3 C3 Output O Output driven waveform 4 C2 Reset I Negative pulse applied to this pin to disable or reset the timer. When not used for reset purposes, it should be connected to VCC to avoid false triggering 5 C1 Control I Control voltage controls the threshold and trigger levels. It determines the pulse Voltage width of the output waveform. An external voltage applied to this pin can also be used to modulate the output waveform 6 B1 Threshold I Compares the voltage applied to the terminal with a reference voltage of 2/3 Vcc. The amplitude of voltage applied to this terminal is responsible for the set state of the flip-flop. 7 A1 Discharge I Open collector output which discharges a capacitor between intervals (in phase with output). It toggles the output from high to low when voltage reaches 2/3 of the supply voltage 8 A2 V+ I Supply voltage with respect to GND Copyright © 2000–2016, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LMC555 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics 7 Parameter Measurement Information 8 Detailed Description 8.1 Overview 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Low-Power Dissipation 8.3.2 Various Packages and Compatibility 8.3.3 Operates in Both Astable and Monostable Mode 8.4 Device Functional Modes 8.4.1 Monostable Operation 8.4.2 Astable Operation 9 Application and Implementation 9.1 Application Information 9.2 Typical Application 9.2.1 Design Requirements 9.2.2 Detailed Design Procedure 9.2.3 Application Curve 9.3 Frequency Divider 9.3.1 Design Requirements 9.3.2 Application Curve 9.4 Pulse Width Modulator 9.4.1 Design Requirements 9.4.2 Application Curve 9.5 Pulse Position Modulator 9.5.1 Design Requirements 9.5.2 Application Curve 9.6 50% Duty Cycle Oscillator 9.6.1 Design Requirements 10 Power Supply Recommendations 11 Layout 11.1 Layout Guidelines 11.2 Layout Example 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates 12.2 Community Resources 12.3 Trademarks 12.4 Electrostatic Discharge Caution 12.5 Glossary 13 Mechanical, Packaging, and Orderable Information