Datasheet LMC555 (Texas Instruments) - 5

LMC555 www.ti.com
SNAS558M – FEBRUARY 2000 – REVISED JULY 2016
6.5 Electrical Characteristics
Test Circuit, T = 25°C, all switches open, RESET to VS unless otherwise noted(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IS Supply Current VS = 1.5 V 50 150 VS = 5 V 100 250 µA VS = 12 V 150 400 VCTRL Control Voltage VS = 1.5 V 0.8 1.0 1.2 VS = 5 V 2.9 3.3 3.8 V VS = 12 V 7.4 8.0 8.6 VDIS Discharge Saturation Voltage VS = 1.5 V, IDIS = 1 mA 75 150 mV VS = 5 V, IDIS = 10 mA 150 300 VOL Output Voltage (Low) VS = 1.5 V, IO = 1 mA 0.2 0.4 VS = 5 V, IO = 8 mA 0.3 0.6 V VS = 12 V, IO = 50 mA 1.0 2.0 VOH Output Voltage VS = 1.5 V, IO = −0.25 mA 1.0 1.25 (High) VS = 5 V, IO = −2 mA 4.4 4.7 V VS = 12 V, IO = −10 mA 10.5 11.3 VTRIG Trigger Voltage VS = 1.5V 0.4 0.5 0.6 V VS = 12V 3.7 4.0 4.3 ITRIG Trigger Current VS = 5V 10 pA VRES Reset Voltage VS = 1.5 V (2) 0.4 0.7 1.0 V VS = 12 V 0.4 0.75 1.1 IRES Reset Current VS = 5 V 10 pA ITHRESH Threshold Current VS = 5 V 10 pA IDIS Discharge Leakage VS = 12 V 1.0 100 nA t Timing Accuracy SW 2, 4 Closed VS = 1.5 V 0.9 1.1 1.25 ms VS = 5 V 1.0 1.1 1.20 VS = 12 V 1.0 1.1 1.25 Δt/ΔVS Timing Shift with Supply VS = 5V ± 1 V 0.3% V Δt/ΔT Timing Shift with Temperature VS = 5 V 75 ppm/°C fA Astable Frequency SW 1, 3 Closed, VS = 12 V 4.0 4.8 5.6 kHz fMAX Maximum Frequency Max. Freq. Test Circuit, VS = 5 V 3.0 MHz tR, tF Output Rise and Max. Freq. Test Circuit 15 ns Fall Times VS = 5V, CL = 10 pF tPD Trigger Propagation Delay VS = 5 V, Measure Delay 100 ns from Trigger to Output (1) All voltages are measured with respect to the ground pin, unless otherwise specified. (2) If the RESET pin is to be used at temperatures of −20°C and below VS is required to be 2.0 V or greater. Copyright © 2000–2016, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LMC555 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics 7 Parameter Measurement Information 8 Detailed Description 8.1 Overview 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Low-Power Dissipation 8.3.2 Various Packages and Compatibility 8.3.3 Operates in Both Astable and Monostable Mode 8.4 Device Functional Modes 8.4.1 Monostable Operation 8.4.2 Astable Operation 9 Application and Implementation 9.1 Application Information 9.2 Typical Application 9.2.1 Design Requirements 9.2.2 Detailed Design Procedure 9.2.3 Application Curve 9.3 Frequency Divider 9.3.1 Design Requirements 9.3.2 Application Curve 9.4 Pulse Width Modulator 9.4.1 Design Requirements 9.4.2 Application Curve 9.5 Pulse Position Modulator 9.5.1 Design Requirements 9.5.2 Application Curve 9.6 50% Duty Cycle Oscillator 9.6.1 Design Requirements 10 Power Supply Recommendations 11 Layout 11.1 Layout Guidelines 11.2 Layout Example 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates 12.2 Community Resources 12.3 Trademarks 12.4 Electrostatic Discharge Caution 12.5 Glossary 13 Mechanical, Packaging, and Orderable Information