Datasheet RX74M (Renesas)

Features Datasheet RX74M Group Renesas MCUs R01DS0433EJ0110 Rev.1.10 600-MHz 32-bit RX MCU, on-chip double-precision floating-point coprocessor, 3604 CoreMark, Jul 31, 2026 arithmetic unit for trigonometric functions, up to 1-MB code MRAM (supporting the dual bank function), 1.5-MB SRAM, EtherCAT slave controller, Ethernet switch module supporting TSN, SD/MMC host interface, expanded serial peripheral interfaces, various communications interfaces including CAN FD, 16-bit A/D converters, RTC, encryption functions, serial sound interfaces Features
■ 32-bit RXv3e CPU core
PLQP0176KJ-A 24 × 24 mm, 0.5-mm pitch Maximum operating frequency: 600 MHz PLQP0144KA-B 20 × 20 mm, 0.5-mm pitch Capable of 3604 CoreMark performance in operation at 600 MHz PLQP0100KP-A 14 × 14 mm, 0.5-mm pitch 64-bit double-precision IEEE-754 floating point A collective register bank save function is available. Supports memory-protection units (MPUs) JTAG, SWD, and FINE (one-line) debugging interfaces PLBG0320GD-A 17 × 17 mm, 0.8-mm pitch PLBG0224GE-A 13 × 13 mm, 0.8-mm pitch Supports the Protect Zone function PLBG0176GG-A 13 × 13 mm, 0.8-mm pitch Instruction cache and data cache: 32 Kbytes each; support for ECC Two local RAMs: 128 Kbytes each; support for ECC
■ Low-power design and architecture ■ Various communications interfaces
Operation from a single 1.62- to 3.63-V supply EtherCAT slave controller with two ports The RTC and backup registers are capable of operation from a battery Two Ethernet MAC units for transfer at up to 1 Gbps, Ethernet switch power supply. module with two ports, support for Ethernet TSN Seven low power consumption modes One high-speed USB 2.0 port for host/function, OTG controller, or BC 1.2,
■ On-chip user extra MRAM
with on-chip PHY layer One full-speed USB 2.0 port for host/function or OTG controller, with on- 128 Kbytes (switchable to operate as MTJ-OTP memory) chip PHY layer User code is programmable by on-board or off-board programming. Three CAN FD modules compliant with the specifications of ISO Capable of holding the user boot program, data, etc. 11898-1:2015
■ On-chip code MRAM
13 RSCIs with 16-byte transmission and reception FIFO buffers The serial communications mode can be selected from among Devices with up to 1 Mbyte are available. asynchronous, clock synchronous, smart card interface, simple SPI, No wait cycles when the prefetch buffer is hit simple I2C, and extended serial. Supports reading at 100 MHz Communications in Manchester code available, support for HBS User code is programmable by on-board or off-board programming. functionality Programming as a background operation (BGO) A dual-bank structure allows swapping the start-up bank. Two I2C-bus interfaces for transfer at up to 3.4 Mbps I3C bus interface for transfer at up to 12 Mbps in SDR mode
■ On-chip data MRAM
Three RSPIAs with single I/O for transmission and reception at up to 50 48 Kbytes; programmable up to 100,000 times Mbps Programming as a background operation (BGO) Parallel data capture unit (PDC) for the CMOS camera interface SD/MMC host interface with a 1- or 4-bit SD bus for use with SD memory
■ On-chip SRAM
or SDIO 1.5 Mbytes; support for ECC and reading at 150 MHz Two SSIEs for various audio formats such as I2S Two XSPIs for transfer at up to 266 MT/s, switchable between controller
■ Data transfer
and target, support for 1-, 2-, 4-, and 8-bit protocols and decryption on the Eight DMA controllers (DMACs), DTCA, two EXDMA controllers fly (DOTF) (EXDMACs), Ethernet DMAC (GWCA), and two XSPIs serving as target PDM-IF connectable with an external microphone modules
■ Up to 26 extended-function timers ■ Reset and supply management
16 32-bit general PWM timers (GPTWs), two 8-bit timers (TMRs) with 2 Power-on reset (POR) channels per unit, two 16-bit CMTs with 2 channels per unit, two 32-bit Programmable voltage detection (PVD) compare match timers W (CMTWs) with a single channel per unit Core voltage monitoring (CVM)
■ Three 16-bit A/D converters
Temperature monitoring reset Backup area reset Up to 36 analog input channels Reset output function Self-diagnosis, detection of analog input disconnection
■ Clock functions ■ Two 12-bit D/A converters
Main clock oscillator for an 8- to 48-MHz external resonator
■ Temperature sensor for measuring temperature
Sub-clock oscillator for a 32.768-kHz crystal resonator
within the chip
Two PLL circuits 8-MHz MOCO, HOCO with 16, 18, 20, 32, or 48 MHz selectable, and
■ Arithmetic unit for trigonometric functions
32.768-kHz LOCO Clock output function
■ Two DSMIFs with 3 channels per unit, connectable with up to six external delta-sigma modulators ■ Realtime clock
Adjustment functions (for 30 seconds, leap year, and time error)
■ Two phase-counting interfaces
Realtime clock counting and binary counting modes are selectable.
■ Security features
Time capture in response to event-signal input Renesas Secure IP (RSIP-E50D) (true-random number generator (TRNG),
■ Independent watchdog timer
AES, ChaCha20-Poly1305, RSA, ECC, SHA-512, SHA3-512, and 128-bit Operation at 16.384 kHz. Operation in deep software standby mode 1 is unique ID) possible. Zeroization Device lifecycle management
■ Useful functions for IEC60730 compliance
Support for decryption on the fly (DOTF) Oscillation stop detection (MOSC, SOSC), clock frequency accuracy Secure boot measurement circuits, CRCA, IWDTa, DOCA, self-diagnosis and Detection of tampering disconnection detection assist functions for the A/D converters, etc. The security attribute is specifiable per pin. Register write protection function protects important registers against Protect Zone function overwriting.
■ Up to 197 pins for general I/O ports ■ External address space
5-V tolerance, open drain, input pull-up, switchable driving ability Buses for high-speed data transfer (max. operating frequency of 80 MHz) Software configurable 32-bit programmable I/O port 8 CS areas with 8-, 16-, or 32-bit bus space selectable per area
■ Operating temperature range
Independent SDRAM area (128 Mbytes) and XSPI areas (1 Gbyte) Tj = –40 to +125C R01DS0433EJ0110 Rev.1.10 Page 1 of 299 Jul 31, 2026 Document Outline Features 1. Overview 1.1 Outline of Specifications 1.2 List of Products 1.3 Block Diagram 1.4 Pin Functions 1.5 Pin Assignments 1.5.1 320-Pin LFBGA 1.5.2 224-Pin LFBGA 1.5.3 176-Pin LFBGA 1.5.4 176-Pin LFQFP 1.5.5 144-Pin LFQFP 1.5.6 100-Pin LFQFP 1.6 List of Pin and Pin Functions 1.6.1 320-Pin LFBGA 1.6.2 224-Pin LFBGA 1.6.3 176-Pin LFBGA 1.6.4 176-Pin LFQFP 1.6.5 144-Pin LFQFP 1.6.6 100-Pin LFQFP 2. Electrical Characteristics 2.1 Test Conditions 2.1.1 Maximum and Minimum Values (Max./Min.) 2.1.2 Typical Values (Typ.) 2.2 Absolute Maximum Ratings 2.3 Recommended Operating Conditions 2.4 DC Characteristics 2.4.1 Characteristics of the Input Voltage of the I/O Pins 2.4.2 Characteristics of the Output Voltage of the I/O Pins 2.4.3 Characteristics of the Other I/O Pins 2.4.4 Operating and Standby Currents 2.4.4.1 Operating and Standby Currents for Product Part No. R5K574Mxy4xx (y = A, B, C, D, T, U, V, W) 2.4.4.2 Operating and Standby Currents for Product Part No. R5K574Mxy4xx (y = E, F) 2.4.4.3 Currents in Deep Software Standby Mode 2.4.4.4 Other Operating Currents 2.4.4.5 Permissible Output Currents 2.4.5 Thermal Characteristics 2.4.5.1 Thermal Resistance Value 2.4.5.2 Supply Currents for the Peripheral Functions 2.4.5.3 Example of Calculation of Ta 2.4.6 VCC Rising and Falling Slopes and Ripple Frequency 2.5 AC Characteristics 2.5.1 Operating Frequency 2.5.2 Clock Timing 2.5.3 Reset Timing 2.5.4 Timing of Return from Low Power Consumption Modes 2.5.5 Control Signal Timing 2.5.6 Bus Timing 2.5.7 Timing of On-Chip Peripheral Modules 2.5.7.1 I/O Port 2.5.7.2 TMR 2.5.7.3 CMTW 2.5.7.4 POEG 2.5.7.5 GPTW 2.5.7.6 RSCI 2.5.7.7 RSPIA 2.5.7.8 XSPI 2.5.7.9 RIICHS 2.5.7.10 RI3C 2.5.7.11 SSIE 2.5.7.12 SD/MMC Host Interface 2.5.7.13 PDC 2.5.7.14 HRPWM 2.5.7.15 CANFD/CANFDG 2.5.7.16 ESC 2.5.7.17 ESWM 2.5.7.18 PDMIF 2.5.7.19 Δ-Σ Interface 2.5.7.20 PCIF 2.5.7.21 PIO 2.5.7.22 A/D Converter Trigger 2.5.7.23 CAC 2.6 USB Characteristics 2.6.1 USB Timing 2.6.2 USBHS Timing 2.7 A/D Conversion Characteristics 2.7.1 Analog Input Voltage Range 2.7.2 Common Characteristics of the 16-Bit A/D Converter 2.7.3 SAR Mode Characteristics 2.7.4 Common Characteristics of Oversampling Mode and Hybrid Mode 2.7.5 Oversampling Mode Characteristics 2.7.6 Hybrid Mode Characteristics 2.8 D/A Conversion Characteristics 2.9 Temperature Sensor Characteristics 2.10 Power-on Reset Circuit and Voltage Detection Circuit Characteristics 2.11 Core Voltage Monitoring Reset Characteristics 2.12 Oscillation Stop Detection Timing 2.13 External VDD Timing Characteristics 2.14 Battery Backup Function Characteristics 2.15 MRAM Characteristics 2.15.1 Code MRAM Characteristics 2.15.2 Option-Setting Memory (MRAM Area) Characteristics 2.15.3 Option-Setting Memory (OTP Area with ECC) Characteristics 2.15.4 Option-Setting Memory (OTP Area without ECC) Characteristics 2.15.5 MACI Command Characteristics 2.15.6 W-HUK Zeroization Characteristics 2.15.7 MRAM Magnetic Field Resistance Characteristics 2.15.8 Data MRAM Characteristics 2.16 Boundary Scan 2.17 Usage Note 2.17.1 Connecting VCL Capacitor and Bypass Capacitors Appendix 1. Package Dimensions REVISION HISTORY General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products Notice