Datasheet SG3525A (ON Semiconductor) - 6
| 制造商 | ON Semiconductor |
| 描述 | PWM Controller |
| 页数 / 页 | 10 / 6 — SG3525A. Figure 3. Oscillator Charge Time versus RT. Figure 4. Oscillator … |
| 文件格式/大小 | PDF / 384 Kb |
| 文件语言 | 英语 |
SG3525A. Figure 3. Oscillator Charge Time versus RT. Figure 4. Oscillator Discharge Time versus RD
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SG3525A
200 500 100 400 ) OR () (k 50 OR 300 * RD = 0 W 20 RESIST TIME RESIST 200 10 6 5 7 , DEAD , TIMING RD * D 100 T 5.0 R R RT CT 2.0 0 2.0 5.0 10 20 50 100 200 500 1000 2000 5000 10,000 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 CHARGE TIME (ms) DISCHARGE TIME (ms)
Figure 3. Oscillator Charge Time versus RT Figure 4. Oscillator Discharge Time versus RD
1 9 - 2 + VCC = +20 V C 4.0 P TJ = +25C 100 RZ 3.5 TAGE (V) 80 3.0 60 2.5 TAGE GAIN (dB) RZ = 20 k TION VOL 2.0 40 , VOL TURA 1.5 Source Sat, (VC-VOH) 20 VOL , SA 1.0 A 0 sat Sink Sat, (V V OL) 0.5 -20 0 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 0.01 0.02 0.03 0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 f, FREQUENCY (Hz) IO, OUTPUT SOURCE OR SINK CURRENT (A)
Figure 5. Error Amplifier Open Loop Figure 6. Output Saturation Frequency Response Characteristics
Vref 15 16 VCC Q1 Q5 Q8 7.4k Q3 RT Q3 6 CT Q6 Q9 5 Ramp Q4 Inverting 2.0k 14k To PWM Q1 Q2 Input 3 2.0k Q10 Q11 25k 1 Sync Blanking Noninverting To PWM 5.0pF 7 To Output Q14 Input Comparator Discharge 400mA 2 Q4 Q2 5.8V 23k 200mA 100mA 30 Q7 1.0k Q12 Q13 250 3.0k 12 1.0k 9 Compensation GND 4 OSC Output
Figure 7. Oscillator Schematic Figure 8. Error Amplifier Schematic www.onsemi.com Share Feedback 6
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200 500 100 400 ) OR () (k 50 OR 300 * RD = 0 W 20 RESIST TIME RESIST 200 10 6 5 7 , DEAD , TIMING RD * D 100 T 5.0 R R RT CT 2.0 0 2.0 5.0 10 20 50 100 200 500 1000 2000 5000 10,000 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 CHARGE TIME (ms) DISCHARGE TIME (ms)
Figure 3. Oscillator Charge Time versus RT Figure 4. Oscillator Discharge Time versus RD
1 9 - 2 + VCC = +20 V C 4.0 P TJ = +25C 100 RZ 3.5 TAGE (V) 80 3.0 60 2.5 TAGE GAIN (dB) RZ = 20 k TION VOL 2.0 40 , VOL TURA 1.5 Source Sat, (VC-VOH) 20 VOL , SA 1.0 A 0 sat Sink Sat, (V V OL) 0.5 -20 0 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 0.01 0.02 0.03 0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 f, FREQUENCY (Hz) IO, OUTPUT SOURCE OR SINK CURRENT (A)
Figure 5. Error Amplifier Open Loop Figure 6. Output Saturation Frequency Response Characteristics
Vref 15 16 VCC Q1 Q5 Q8 7.4k Q3 RT Q3 6 CT Q6 Q9 5 Ramp Q4 Inverting 2.0k 14k To PWM Q1 Q2 Input 3 2.0k Q10 Q11 25k 1 Sync Blanking Noninverting To PWM 5.0pF 7 To Output Q14 Input Comparator Discharge 400mA 2 Q4 Q2 5.8V 23k 200mA 100mA 30 Q7 1.0k Q12 Q13 250 3.0k 12 1.0k 9 Compensation GND 4 OSC Output
Figure 7. Oscillator Schematic Figure 8. Error Amplifier Schematic www.onsemi.com Share Feedback 6
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