Datasheet SG3525A (ON Semiconductor)
| 制造商 | ON Semiconductor |
| 描述 | PWM Controller |
| 页数 / 页 | 10 / 1 — DATA SHEET. Share Feedback. www.onsemi.com. MARKING. DIAGRAMS. PDIP−16. N … |
| 文件格式/大小 | PDF / 384 Kb |
| 文件语言 | 英语 |
DATA SHEET. Share Feedback. www.onsemi.com. MARKING. DIAGRAMS. PDIP−16. N SUFFIX. CASE 648−08. SOIC−16 WB. DW SUFFIX. CASE 751G
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Pulse Width Modulator
MARKING DIAGRAMS
Control Circuit 16 SG3525A
PDIP−16
SG3525AN
N SUFFIX
AWLYYWW The SG3525A pulse width modulator control circuit offers 16
CASE 648−08
1 improved performance and lower external parts count when 1 implemented for controlling all types of switching power supplies. 16 The on−chip +5.1 V reference is trimmed to "1% and the error amplifier has an input common−mode voltage range that includes the
SOIC−16 WB
reference voltage, thus eliminating the need for external divider 16 SG3525A
DW SUFFIX
resistors. A sync input to the oscillator enables multiple units to be AWLYYWW
CASE 751G
slaved or a single unit to be synchronized to an external system clock. 1 A wide range of deadtime can be programmed by a single resistor 1 connected between the CT and Discharge pins. This device also features built−in soft−start circuitry, requiring only an external timing A = Assembly Location capacitor. A shutdown pin controls both the soft−start circuitry and the WL = Wafer Lot output stages, providing instantaneous turn off through the PWM latch YY = Year with pulsed shutdown, as well as soft−start recycle with longer WW = Work Week shutdown commands. The under voltage lockout inhibits the outputs and the changing of the soft−start capacitor when VCC is below nominal. The output stages are totem−pole design capable of sinking
PIN CONNECTIONS
and sourcing in excess of 200 mA. The output stage of the SG3525A features NOR logic resulting in a low output for an off−state. Inv. Input 1 16 Vref
Features
Noninv. Input 2 15 VCC 8.0 V to 35 V Operation Sync 3 14 Output B 5.1 V " 1.0% Trimmed Reference OSC. Output 4 13 VC 100 Hz to 400 kHz Oscillator Range CT 5 12 Ground Separate Oscillator Sync Pin R Adjustable Deadtime Control T 6 11 Output A Input Undervoltage Lockout Discharge 7 10 Shutdown Latching PWM to Prevent Multiple Pulses Soft-Start 8 9 Compensation Pulse−by−Pulse Shutdown Dual Source/Sink Outputs: "400 mA Peak (Top View) Pb−Free Packages are Available*
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the
onsemi
Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
February, 2024 − Rev. 7 SG3525A/D
DATA SHEET Share Feedback
Your Opinion Matters
www.onsemi.com
Pulse Width Modulator
MARKING DIAGRAMS
Control Circuit 16 SG3525A
PDIP−16
SG3525AN
N SUFFIX
AWLYYWW The SG3525A pulse width modulator control circuit offers 16
CASE 648−08
1 improved performance and lower external parts count when 1 implemented for controlling all types of switching power supplies. 16 The on−chip +5.1 V reference is trimmed to "1% and the error amplifier has an input common−mode voltage range that includes the
SOIC−16 WB
reference voltage, thus eliminating the need for external divider 16 SG3525A
DW SUFFIX
resistors. A sync input to the oscillator enables multiple units to be AWLYYWW
CASE 751G
slaved or a single unit to be synchronized to an external system clock. 1 A wide range of deadtime can be programmed by a single resistor 1 connected between the CT and Discharge pins. This device also features built−in soft−start circuitry, requiring only an external timing A = Assembly Location capacitor. A shutdown pin controls both the soft−start circuitry and the WL = Wafer Lot output stages, providing instantaneous turn off through the PWM latch YY = Year with pulsed shutdown, as well as soft−start recycle with longer WW = Work Week shutdown commands. The under voltage lockout inhibits the outputs and the changing of the soft−start capacitor when VCC is below nominal. The output stages are totem−pole design capable of sinking
PIN CONNECTIONS
and sourcing in excess of 200 mA. The output stage of the SG3525A features NOR logic resulting in a low output for an off−state. Inv. Input 1 16 Vref
Features
Noninv. Input 2 15 VCC 8.0 V to 35 V Operation Sync 3 14 Output B 5.1 V " 1.0% Trimmed Reference OSC. Output 4 13 VC 100 Hz to 400 kHz Oscillator Range CT 5 12 Ground Separate Oscillator Sync Pin R Adjustable Deadtime Control T 6 11 Output A Input Undervoltage Lockout Discharge 7 10 Shutdown Latching PWM to Prevent Multiple Pulses Soft-Start 8 9 Compensation Pulse−by−Pulse Shutdown Dual Source/Sink Outputs: "400 mA Peak (Top View) Pb−Free Packages are Available*
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the
onsemi
Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
February, 2024 − Rev. 7 SG3525A/D