Datasheet TB9M040FTG (Toshiba) - 7
| 制造商 | Toshiba |
| 描述 | IC for automotive three-phase brushless DC motor in 36-VFQFPN package |
| 页数 / 页 | 38 / 7 — Preliminary. 9. Functional Description 9.1. Bridge Drivers (BDRV) … |
| 文件格式/大小 | PDF / 1.0 Mb |
| 文件语言 | 英语 |
Preliminary. 9. Functional Description 9.1. Bridge Drivers (BDRV) Circuit. Figure 9.1.1 BDRV Circuit Diagram
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Preliminary
TB9M040FTG
9. Functional Description 9.1. Bridge Drivers (BDRV) Circuit
This is a three-phase inverter circuit (high-side Nch MOSFET / low-side Nch MOSFET) for driving a BLDC motor. (Maximum output current capability: 2A) The ON/OFF control is performed according to the drive signals from the digital circuit. Abnormal conditions are detected when the VDS of the built‑in FET rises while the FET is ON (HSVDSDET, LSVDSDET). HSVDSDET can be enabled or disabled via register settings (flag output only). LSVDSDET can be enabled or disabled via register settings. When disabled, the flag is not asserted. When OCCMP, HSVDSDET, or LSVDSDET is detected, BDRV output is set to Hi-Z state for protection (forced off). A back-EMF position detection circuit using a virtual neutral point method is integrated. VBATD VBATD Enable/Disable [CGPER] VCP <CGPEN> CGP BIAS Enable [BDRVBIASER] <BDRVBIASEN> Bias reference circuits Enable/Disable [BDRVER] <BDRVEN> High Side UOx PREDRV VOx WOx PMD XOx S/R Control [BDRVSRCR] YOx ZOx <BDRVSRC> U U To HSVDSCMP V To LSVDSCMP W VCC To ENC BEMFCMP Low Side COM PREDRV S/R Control [BDRVSRCR] <BDRVSRC> VCC To OCCMP,CLCMP,MADC CSAMP 0.1Ω(Typ.) Rshunt GNDP Offset, Gain Enable,Disable [CSAMPSR] [CSAMPER] Calibration <OUTOFFSET> <CSAMPEN> [CSAMPCAL] <GAIN> <CALIBSET>
Figure 9.1.1 BDRV Circuit Diagram
© 2 026 7 2026-3-26 Toshiba Electronic Devices & Storage Corporation Rev. 1.0 Document Outline 1. Description 2. Applications 3. Features 4. Functions 5. Block Diagram 6. Pin Assignments 7. Pin Description 8. I/O Equivalent Circuits 9. Functional Description 9.1. Bridge Drivers (BDRV) Circuit 9.2. High Side Driver (HSD) 9.3. Current-Sense Amplifier (CSAMP) 9.4. Current Limit Comparator (CLCMP) 9.5. Overcurrent Detection Comparator (OCCMP) 9.6. Vector Engine(VE) 9.7. Programmable Motor Driver (PMD) 9.8. Memory Map 10. Electrical Characteristics 10.1. Absolute Maximum Ratings 10.2. Operating Ranges 10.3. Overall Electrical Characteristics 10.4. Reset Generator and Standby Time 10.5. 5-V Regulator (LDO5V) 10.6. 1.5-V Regulator (LDO15V) 10.7. Charge Pump 10.8. Oscillator 10.9. 12-bit ADC 10.10. Bridge Drivers (BRDV) 10.11. Current-Sense Amplifier (CSAMP) 10.12. Current Limit Comparator (CLCMP) 10.13. Overcurrent Detection Comparator (OCCMP) 10.14. Back-EMF Comparator (BEMFCMP) 10.15. Thermal Shutdown (TSD) Circuit 10.16. LIN 10.17. UART 10.18. SPI 10.19. GPIO 10.20. Flash (Code Flash) 10.21. Other 11. Application Circuit Example 12. Package Information 12.1. Package Dimensions 12.2. Marking 13. IC Usage Considerations 13.1. Notes on Handling of ICs 13.2. Points to Remember on Handling of ICs RESTRICTIONS ON PRODUCT USE
TB9M040FTG
9. Functional Description 9.1. Bridge Drivers (BDRV) Circuit
This is a three-phase inverter circuit (high-side Nch MOSFET / low-side Nch MOSFET) for driving a BLDC motor. (Maximum output current capability: 2A) The ON/OFF control is performed according to the drive signals from the digital circuit. Abnormal conditions are detected when the VDS of the built‑in FET rises while the FET is ON (HSVDSDET, LSVDSDET). HSVDSDET can be enabled or disabled via register settings (flag output only). LSVDSDET can be enabled or disabled via register settings. When disabled, the flag is not asserted. When OCCMP, HSVDSDET, or LSVDSDET is detected, BDRV output is set to Hi-Z state for protection (forced off). A back-EMF position detection circuit using a virtual neutral point method is integrated. VBATD VBATD Enable/Disable [CGPER] VCP <CGPEN> CGP BIAS Enable [BDRVBIASER] <BDRVBIASEN> Bias reference circuits Enable/Disable [BDRVER] <BDRVEN> High Side UOx PREDRV VOx WOx PMD XOx S/R Control [BDRVSRCR] YOx ZOx <BDRVSRC> U U To HSVDSCMP V To LSVDSCMP W VCC To ENC BEMFCMP Low Side COM PREDRV S/R Control [BDRVSRCR] <BDRVSRC> VCC To OCCMP,CLCMP,MADC CSAMP 0.1Ω(Typ.) Rshunt GNDP Offset, Gain Enable,Disable [CSAMPSR] [CSAMPER] Calibration <OUTOFFSET> <CSAMPEN> [CSAMPCAL] <GAIN> <CALIBSET>
Figure 9.1.1 BDRV Circuit Diagram
© 2 026 7 2026-3-26 Toshiba Electronic Devices & Storage Corporation Rev. 1.0 Document Outline 1. Description 2. Applications 3. Features 4. Functions 5. Block Diagram 6. Pin Assignments 7. Pin Description 8. I/O Equivalent Circuits 9. Functional Description 9.1. Bridge Drivers (BDRV) Circuit 9.2. High Side Driver (HSD) 9.3. Current-Sense Amplifier (CSAMP) 9.4. Current Limit Comparator (CLCMP) 9.5. Overcurrent Detection Comparator (OCCMP) 9.6. Vector Engine(VE) 9.7. Programmable Motor Driver (PMD) 9.8. Memory Map 10. Electrical Characteristics 10.1. Absolute Maximum Ratings 10.2. Operating Ranges 10.3. Overall Electrical Characteristics 10.4. Reset Generator and Standby Time 10.5. 5-V Regulator (LDO5V) 10.6. 1.5-V Regulator (LDO15V) 10.7. Charge Pump 10.8. Oscillator 10.9. 12-bit ADC 10.10. Bridge Drivers (BRDV) 10.11. Current-Sense Amplifier (CSAMP) 10.12. Current Limit Comparator (CLCMP) 10.13. Overcurrent Detection Comparator (OCCMP) 10.14. Back-EMF Comparator (BEMFCMP) 10.15. Thermal Shutdown (TSD) Circuit 10.16. LIN 10.17. UART 10.18. SPI 10.19. GPIO 10.20. Flash (Code Flash) 10.21. Other 11. Application Circuit Example 12. Package Information 12.1. Package Dimensions 12.2. Marking 13. IC Usage Considerations 13.1. Notes on Handling of ICs 13.2. Points to Remember on Handling of ICs RESTRICTIONS ON PRODUCT USE