Datasheet EPC23108 (Efficient Power Conversion) - 2
| 制造商 | Efficient Power Conversion |
| 描述 | 100V, 35 A ePower Stage IC |
| 页数 / 页 | 17 / 2 — eGaN® IC DATASHEET. Figure 2: EPC23108 Quad Flat No-Lead (QFN). Package … |
| 文件格式/大小 | PDF / 2.0 Mb |
| 文件语言 | 英语 |
eGaN® IC DATASHEET. Figure 2: EPC23108 Quad Flat No-Lead (QFN). Package (Transparent Top View). EPC23108 Pinout Description
该数据表的模型线
文件文字版本
eGaN® IC DATASHEET
EPC23108
Figure 2: EPC23108 Quad Flat No-Lead (QFN) Package (Transparent Top View) EPC23108 Pinout Description Pin Pin Name Pin Type Description 1
HSIN L High-side PWM logic input referenced to AGND. Internal pull-down resistor is connected between HSIN and AGND.
2
LSIN L Low-side PWM logic input referenced to AGND. Internal pull-down resistor is connected between LS
10 9 8
IN and AGND. VDD standby and PWM fast shutdown input. Internal VDD is disabled when
3
SD/STB L (SD/STB) is pulled down or driven low. Internal pull-up resistor disables the standby function by default. If (SD/STB) is pulled low, the PWM inputs are immediately inhibited, and both power GaN FETs are switched OFF
4
VDD S Internal power supply referenced to AGND, connect a bypass capacitor from VDD to AGND.
7 5
VDRV S External 5 V power supply referenced to AGND, connect a bypass capacitor from VDRV to AGND.
11 6 6
RDRV G Insert a resistor between RDRV and VDRV to control the turn-on slew rate of the low-side FET.
12 7
AGND S Logic ground. AGND is internally connected to PGND.
13 1 2 3 4 5 8
PGND P Power ground. Connected to the source terminal of the low-side FET.
9
SW P Switching node. Connected to half-bridge power stage output.
Transparent Top View 10
VIN P Power DC input. Connected to drain terminal of the high-side FET. Connect power loop capacitors from VIN to PGND.
11
VPHASE S VPHASE is Kelvin connected to SW. Used as ground return for the bootstrap capacitor CBOOT.
12
RBOOT G Insert a resistor between RBOOT and VBOOT to control the turn-on slew rate of the high-side FET.
13
VBOOT S Floating bootstrap power supply referenced to VPHASE (=SW). Connect an external bootstrap capacitor, CBOOT, between VBOOT and VPHASE. Pin Type: P = Power, S = Bias Supplies, L = Logic Inputs/Outputs, G = Gate Drive Adjust Notes: • The standby function can be disabled by tying VDD to VDRV. In this case, only the PWM fast shutdown function is enabled. • AGND and PGND are internally connected. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2026 | For more information: info@epc-co.com | 2
EPC23108
Figure 2: EPC23108 Quad Flat No-Lead (QFN) Package (Transparent Top View) EPC23108 Pinout Description Pin Pin Name Pin Type Description 1
HSIN L High-side PWM logic input referenced to AGND. Internal pull-down resistor is connected between HSIN and AGND.
2
LSIN L Low-side PWM logic input referenced to AGND. Internal pull-down resistor is connected between LS
10 9 8
IN and AGND. VDD standby and PWM fast shutdown input. Internal VDD is disabled when
3
SD/STB L (SD/STB) is pulled down or driven low. Internal pull-up resistor disables the standby function by default. If (SD/STB) is pulled low, the PWM inputs are immediately inhibited, and both power GaN FETs are switched OFF
4
VDD S Internal power supply referenced to AGND, connect a bypass capacitor from VDD to AGND.
7 5
VDRV S External 5 V power supply referenced to AGND, connect a bypass capacitor from VDRV to AGND.
11 6 6
RDRV G Insert a resistor between RDRV and VDRV to control the turn-on slew rate of the low-side FET.
12 7
AGND S Logic ground. AGND is internally connected to PGND.
13 1 2 3 4 5 8
PGND P Power ground. Connected to the source terminal of the low-side FET.
9
SW P Switching node. Connected to half-bridge power stage output.
Transparent Top View 10
VIN P Power DC input. Connected to drain terminal of the high-side FET. Connect power loop capacitors from VIN to PGND.
11
VPHASE S VPHASE is Kelvin connected to SW. Used as ground return for the bootstrap capacitor CBOOT.
12
RBOOT G Insert a resistor between RBOOT and VBOOT to control the turn-on slew rate of the high-side FET.
13
VBOOT S Floating bootstrap power supply referenced to VPHASE (=SW). Connect an external bootstrap capacitor, CBOOT, between VBOOT and VPHASE. Pin Type: P = Power, S = Bias Supplies, L = Logic Inputs/Outputs, G = Gate Drive Adjust Notes: • The standby function can be disabled by tying VDD to VDRV. In this case, only the PWM fast shutdown function is enabled. • AGND and PGND are internally connected. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2026 | For more information: info@epc-co.com | 2