Datasheet EPC23108 (Efficient Power Conversion) - 4

eGaN® IC DATASHEET
EPC23108
Electrical Characteristics
Nominal VIN = 48 V, VDRV = VDD = 5 V and (VBOOT – VPHASE) = 5 V. All typical ratings are specifed at TA = 25˚C unless otherwise indicated. All voltage parameters are absolute voltages referenced to PGND unless indicated otherwise. AGND and PGND are internal y connected. Parameters that show only the typical value are guaranteed by design and not tested in production.
Electrical Characteristics SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Low-side Power Supply
OFF state total quiescent current HSIN/LSIN = 0 V, SD/STB = 5 V, SW floating 7 10 13 IDRV_Q HSFET ON state total quiescent current LSIN = 0 V, HSIN /(SD/STB) = 5 V, SW floating 7 10 13 LSFET ON state total quiescent current HSIN = 0 V, LSIN/(SD/STB) = 5 V, SW floating 7 11.5 15 mA IDRV_100kHz Total operating current @100 kHz PWM = 100 kHz, 50% ON-time, includes bootstrap current 18 IDRV_1MHz Total operating current @1 MHz PWM = 1 MHz, 50% ON-time, includes bootstrap current 34
Standby Current
IVIN_standby VIN current in standby mode SD/STB = 0 V 125 160 µA IDRV_standby VDRV current in standby mode SD/STB = 0 V 120 150
Bootstrap Power Supply
I HSIN/LSIN/ = 0 V, SD/STB = 5 V 4 5.5 8 BOOT_Q OFF state bootstrap supply current LSIN/ = 0 V, HSIN/SD/STB = 5 V 6.5 mA IBOOT_100kHz Bootstrap supply current @100 kHz HS PWM = 100 kHz, 50% ON-time 7 IBOOT_1MHz Bootstrap supply current @1 MHz HS PWM = 1 MHz, 50% ON-time 16 RON_SYNC_BOOT ON resistance of sync-boot FET ISYNC_BOOT = 25 mA 1 2 2.6 Ω
Power On Reset
VDD_POR+ POR trip level VDD rising LSIN = 5 V, VDD ramps up 4.25 VDD_POR_HYST POR VDD falling hysteresis LSIN = 5 V, VDD ramps down 0.15 V VBOOT_POR+ POR trip level (VBOOT - VPHASE) rising HSIN = 5 V, VBOOT ramps up 4.25 VBOOT_POR_HYST POR (VBOOT - VPHASE) falling hysteresis HSIN = 5 V, VBOOT ramps down 0.15
Logic Input Pins
VIH High-level logic threshold HSIN, LSIN rising 2.4 VIL Low-level logic threshold HSIN, LSIN falling 0.8 V VIHYST Logic threshold hysteresis VIH rising – VIL falling 0.3 RIN HSIN and LSIN pull-down resistance HSIN, LSIN = 5 V 5 kΩ
VDD Disable - Standby Function
VSD-STB_H High-level SD/STB logic threshold SD/STB rising 2.4 V VSD-STB_L Low-level SD/STB logic threshold SD/STB falling 0.8 RSTB STB pull-up resistance SD/STB = 0 V 65 kΩ
High-Side Internal Power FET (HS_FET)
RDS(on)_HS High-side FET RDS(on) ISW = +/-1 A, HSIN = 5 V, LSIN = 0 V (2) 5.2 6.6 mΩ VHS_DS_Clamp High-side 3rd quadrant clamp ISW = - 1 A, HSIN = LSIN = 0 V (2) -2.1 -1.7 V VHS_DS_Clamp_0V High-side 3rd quadrant clamp ISW = - 1 A, HSIN = LSIN = 0 V, VBOOT – VPHASE = 0 V (2) -3 COSS_HSFET Output capacitance (VIN to SW) HSIN = 0 V, SW = 0 V 342 pF QOSS_HSFET Output charge (VIN to SW) HSIN = 0 V, SW = 0 V 28 nC EOSS_HSFET Output capacitance stored energy HSIN = 0 V, SW = 0 V 0.5 µJ
Low-Side Internal Power FET (LS_FET)
RDS(on)_LS Low-side FET RDS(on) ISW = +/-1 A, LSIN = 5 V, HSIN = 0 V (2) 5.2 6.6 mΩ VLS_DS_Clamp Low-side 3rd quadrant clamp ISW = 1 A, HSIN = LSIN = 0 V (2) -2.1 -1.7 V VLS_DS_Clamp_0V Low-side 3rd quadrant clamp ISW = 1 A, HSIN = LSIN = 0 V, VDD = 0 V (2) -2.2 COSS_LSFET Output capacitance (SW to PGND) LSIN = 0 V, SW = 48 V 404 pF QOSS_LSFET Output charge (SW to PGND) LSIN = 0 V, SW = 48 V 35 nC EOSS_LSFET Output capacitance stored energy LSIN = 0 V, SW = 48 V 0.6 µJ EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2026 | For more information: info@epc-co.com | 4