Datasheet LTC7890 (Analog Devices) - 8

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LTC7890 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 3. Pin Function Descriptions (Continued) Pin No. Mnemonic Description
13 VFB2 Error Amplifier Feedback Input for Channel 2. VFB2 receives the remotely sensed feedback voltage for Channel 2 from an external resistive divider across the output. Tie VFB2 to INTVCC for a 2-phase single output application, in which both channels share VFB1, ITH1, and TRACK/SS1. 14 ITH2 Error Amplifier Output and Switching Regulator Compensation Point for Channel 2. The current comparator trip point increases with this control voltage. 15 TRACK/SS2 External Tracking/Soft Start Input for Channel 2. TRACK/SS2 regulates the VFB2 voltage to the lesser of 0.8 V or the voltage on the TRACK/SS2 pin. An internal 12 µA pull-up current source is connected to TRACK/SS2. A capacitor to GND at TRACK/SS2 sets the ramp time to the final regulated output voltage. The ramp time is equal to 1 ms for every 12.5 nF of capacitance. Alternatively, a resistor divider on another voltage supply connected to TRACK/SS2 allows the output to track the other supply during startup. 16 ILIM Current Comparator Sense Voltage Range Input. Tying ILIM to GND or INTVCC or floating ILIM sets the maximum current sense threshold to one of three different levels (25 mV, 75 mV, or 50 mV, respectively). 17 PGOOD2 Power-Good Open-Drain Logic Output for Channel 2. PGOOD2 is pulled to GND when the voltage on VFB2 is not within ±10% of its set point. 18 TGUP2 High Current Gate Driver Pull-Up for Top FET for Channel 2. TGUP2 pulls up to BOOST2. Tie TGUP2 directly to the top FET gate for maximum gate drive transition speed on the gate rising edge. Tie a resistor between TGUP2 and the top FET gate to adjust the gate rising slew rate. 19 TGDN2 High Current Gate Driver Pull-Down for Top FET for Channel 2. TGDN2 pulls down to SW2. Tie TGDN2 directly to the top FET gate for maximum gate drive transition speed on the gate falling edge. Tie a resistor between TGDN2 and the top FET gate to adjust the gate falling slew rate. 20 SW2 Switch Node Connection to Inductor for Channel 2. 21 BOOST2 Bootstrapped Supply to the Top Side Floating Driver for Channel 2. Connect a capacitor between the BOOST2 and SW2 pins. An internal switch provides power to the BOOST2 pin from DRVCC when the bottom FET turns on. The voltage swing at the BOOST2 pin is from DRVCC to (VIN + DRVCC). 22 BGDN2 High Current Gate Driver Pull-Down for Bottom FET for Channel 2. BGDN2 pulls down to GND. Tie BGDN2 directly to the bottom FET gate for maximum gate drive transition speed on the gate falling edge. Tie a resistor between BGDN2 and the bottom FET gate to adjust the gate falling slew rate. BGDN2 also serves as the Kelvin sense of the bottom FET gate during turn on. 23 BGUP2 High Current Gate Driver Pull-Up for Bottom FET for Channel 2. BGUP2 pulls up to DRVCC. Tie BGUP2 directly to the bottom FET gate for maximum gate drive transition speed on the gate rising edge. Tie a resistor between BGUP2 and the bottom FET gate to adjust the gate rising slew rate. BGUP2 also serves as the Kelvin sense of the bottom FET gate during turn off. 24 DRVCC Gate Driver Power Supply Pin. The gate drivers are powered from DRVCC. Connect DRVCC to INTVCC by a separate trace to the INTVCC bypass capacitor. 25 INTVCC Output of the Internal LDO Regulator. The INTVCC voltage regulation point is set by the DRVSET pin. INTVCC must be decoupled to GND with a 4.7 µF to 10 µF ceramic or other low equivalent series resistance (ESR) capacitor. 26 EXTVCC External Power Input to an Internal LDO Regulator Connected to DRVCC. This LDO regulator supplies INTVCC power, bypassing the internal VIN LDO regulator whenever EXTVCC is higher than the EXTVCC switchover voltage. See the EXTVCC connection in the Power and Bias Supplies (VIN, EXTVCC, DRVCC, and INTVCC) section and INTVCC Regulators (OPTI-DRIVE) section. Do not exceed 30 V on EXTVCC. Connect EXTVCC to GND if the EXTVCC LDO regulator is not used. 27 VIN Main Supply Pin. A bypass capacitor must be tied between VIN and GND. 28 BGUP1 High Current Gate Driver Pull-Up for Bottom FET for Channel 1. BGUP1 pulls up to DRVCC. Tie BGUP1 directly to the bottom FET gate for maximum gate drive transition speed on the gate rising edge. Tie a resistor between BGUP1 and the bottom FET gate to adjust the gate rising slew rate. BGUP1 also serves as the Kelvin sense of the bottom FET gate during turn off. 29 BGDN1 High Current Gate Driver Pull-Down for Bottom FET for Channel 1. BGDN1 pulls down to GND. Tie BGDN1 directly to the bottom FET gate for maximum gate drive transition speed on the gate falling edge. Tie a resistor between BGDN1 and the bottom FET gate to adjust the gate falling slew rate. BGDN1 also serves as the Kelvin sense of the bottom FET gate during turn on. 30 BOOST1 Bootstrapped Supply to the Top Side Floating Driver for Channel 1. Connect a capacitor between the BOOST1 and SW1 pins. An internal switch provides power to the BOOST1 pin from DRVCC when the bottom FET turns on. The voltage swing at the BOOST1 pin is from DRVCC to (VIN + DRVCC). 31 SW1 Switch Node Connection to Inductor for Channel 1. 32 TGDN1 High Current Gate Driver Pull-Down for Top FET for Channel 1. TGDN1 pulls down to SW1. Tie TGDN1 directly to the top FET gate for maximum gate drive transition speed on the gate falling edge. Tie a resistor between TGDN1 and the top FET gate to adjust the gate falling slew rate. 33 TGUP1 High Current Gate Driver Pull-Up for Top FET for Channel 1. TGUP1 pulls up to BOOST1. Tie TGUP1 directly to the top FET gate for maximum gate drive transition speed on the gate rising edge. Tie a resistor between TGUP1 and the top FET gate to adjust the gate rising slew rate. 34 PGOOD1 Power-Good Open-Drain Logic Output for Channel 1. PGOOD1 is pulled to GND when the voltage on VFB1 is not within ±10% of its set point.
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Document Outline Features Applications Typical Application Circuit General Description Specifications Electrical Characteristics Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Functional Diagram Main Control Loop Power and Bias Supplies (VIN, EXTVCC, DRVCC, and INTVCC) High-Side Bootstrap Capacitor Dead Time Control (DTCA and DTCB Pins) Startup and Shutdown (RUNx and TRACK/SSx Pins) Light Load Operation: Burst Mode Operation, Pulse Skipping Mode, or Forced Continuous Mode (MODE Pin) Frequency Selection, Spread Spectrum, and Phase-Locked Loop (FREQ and PLLIN/SPREAD Pins) Output Overvoltage Protection Foldback Current Power-Good Applications Information Inductor Value Calculation Inductor Core Selection Current Sense Selection Low Value Resistor Current Sensing Inductor DCR Current Sensing Setting the Operating Frequency Selecting the Light Load Operating Mode Dead Time Control (DTCA and DTCB Pins) DTCx Pins Tied to GND (Adaptive Dead Time Control) DTCx Pins Tied to INTVCC (Smart Near Zero Dead Time Control) DTCx Pins Connected with a Resistor to GND Power FET Selection CIN and COUT Selection Setting the Output Voltage RUNx Pins and Undervoltage Lockout Soft Start and Tracking (TRACK/SSx Pin) 2-Phase Single Output Operation INTVCC Regulators (OPTI-DRIVE) Topside FET Driver Supply (CB) Minimum On-Time Considerations Fault Conditions: Current Limit and Foldback Fault Conditions: Overvoltage Protection Fault Conditions: Overtemperature Protection Phase-Locked Loop and Frequency Synchronization Efficiency Considerations Checking Transient Response Design Example PCB Layout Checklist PCB Layout Debugging Typical Applications Related Products Outline Dimensions Ordering Guide Evaluation Boards