Datasheet IP175LLF (IC Plus) - 9
| 制造商 | IC Plus |
| 描述 | 5 Port 10/100 Ethernet Integrated Switch in 68-pin QFN package |
| 页数 / 页 | 116 / 9 — (continued). Pin No. Label. Type. Description. LED pins used as initial … |
| 文件格式/大小 | PDF / 1.5 Mb |
| 文件语言 | 英语 |
(continued). Pin No. Label. Type. Description. LED pins used as initial setting (the setting is latched at the end of reset)
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IP175LLF Datasheet Pin description
(continued) Pin No. Label Type Description LED pins used as initial setting (the setting is latched at the end of reset)
54 LINK_Q IPH1 Link quality 1: enable (default) 0: disable When the function is enabled, besides link on/off status, activity status, link LED shows link quality. The link LED will be flash (on: 2sec / off: 2sec) when the SNR of received signal is lower than the desired value for normal operation. 9/116 April 11, 2018 Copyright © 2007, IC Plus Corp. IP175LLF-DS-R04 Document Outline Comparison Table between IP175D and IP175LLF 1 Pin Diagram 1.1 IP175LLF Pin diagram (QFN68) 2 Pin Description 3 Function Description 3.1 Flow Control 3.2 Broadcast Storm Protection 3.3 Rate Control 3.4 External MII 3.4.1 To define the speed, duplex and pause of MII port 3.4.2 The Application Circuit of RMII 3.5 Virtual LAN (VLAN) 3.5.1 Port-based VLAN 3.5.2 Tag-based VLAN 3.5.3 VLAN Ingress Filtering 3.5.4 Shared and Independent VLAN Learning 3.5.5 The determination of the requirement to insert or remove tag 3.6 Quality of Service (QoS) 3.6.1 Traffic Policy 3.6.2 Priority Classification 3.6.3 Output Queue Scheduling 3.7 Port mirror 3.8 Layer 2-4 Multi-Field Classification 3.9 MAC Address Table 3.9.1 Entry Content 3.9.2 Accessing MAC Table 3.10 CPU Interrupt Control for loop detection 3.11 IGMP Snooping 3.12 Security Filtering 3.12.1 Physical Port Filtering 3.12.2 MAC Address Filtering 3.12.3 Logical Port Filtering 3.12.4 Layer 2-4 Multi-Field Filtering 3.13 IEEE 802.1x 3.14 Spanning Tree 3.15 Special Tag 3.16 Loop Detection 3.17 LED Blink Timing 3.18 Serial Management Interface 3.19 Reset 3.20 Built in regulator 4 PHY Register 4.1 PHY ID Map 4.2 PHY 0~3 and 5 Register Map 4.3 MII Register 0 4.3.1 MII Register 0 of PHY0~3 4.3.2 MII Register 0 of PHY5 4.4 MII Register 1 4.4.1 MII Register 1 of PHY0~3 4.4.2 MII Register 1 of PHY5 4.5 MII Register 2 of PHY0~3 (4 PHYs share the MII register) 4.6 MII Register 3 of PHY0~3 (4 PHYs share the MII register) 4.7 MII Register 4 4.7.1 MII Register 4 of PHY0~3 4.7.2 MII Register 4 of PHY5 4.8 MII Register 5 4.8.1 MII Register 5 of PHY0~3 4.8.2 MII Register 5 of PHY5 4.9 MII Register 6 of PHY0~3 4.10 MII Register 16 of PHY0~3 (4 PHYs share the MII register) 4.11 MII Register 18 of PHY0~3 4.12 MII Register 22 of PHY0~3 (4 PHYs share the MII register) 5 Switch Register 5.1 Switch Register Map 5.2 Switch Register EEPROM Map 5.3 Switch Control Register 5.3.1 Chip Identification 5.3.2 Software Reset Register 5.3.3 MII Force Mode 5.3.4 Congestion Control Register 5.3.5 Port State 5.3.6 Illegal Frame Filter 5.3.7 Special Packet Identification 5.3.7.1 Reserved Address 01-80-C2-00-00-00 to 01-80-C2-00-00-1F 5.3.7.2 Reserved Address 01-80-C2-00-00-20 to 01-80-C2-00-00-FF 5.3.7.3 Miscellaneous Special Packet Identification 5.3.8 Network Security 5.3.9 Learning Control Register 5.3.10 Aging Time Parameter 5.3.11 Broadcast Storm Protection 5.3.12 Port Mirror 5.3.13 Source Block Protection 5.3.14 LED Control Register 5.4 External MII Control Register 5.4.1 External MII Status Report Register 5.4.2 MII0 MAC Mode Register 5.4.3 MII0 Control Register 1 5.4.4 MII0 Control Register 2 5.5 IGMP Control Register 5.5.1 Base Control Register 5.5.2 Router Port Timeout 5.5.3 IGMP Group Timeout 5.6 Rate Control 5.6.1 Basic Rate Setting Register 5.6.2 Rate Setting Access Control Register 5.7 Address Table Access Register 5.7.1 Command Register 5.7.2 Data Buffer Register (For Unicast MAC Address) 5.7.3 Data Buffer Register (For Multicast MAC Address) 5.7.4 Data Buffer Register (For IP Multicast Address) 5.8 CPU Interrupt Register 5.8.1 CPU Interrupt Control Register 5.8.2 Loop detection enable Register 5.8.3 Loop port indicator Register 5.9 Miscellaneous Control Register 5.10 CRC Counter 5.11 VLAN Group Control Register 5.11.1 VLAN Classification 5.11.2 VLAN Ingress Rule 5.11.3 VLAN Egress Rule 5.11.4 Default VLAN Information 5.11.5 VLAN Table 5.11.5.1 VLAN Control Register 5.11.5.2 VLAN Identifier Register 5.11.5.3 VLAN Member Register 5.11.5.4 Add Tag Control Register 5.11.5.5 Remove Tag Control Register 5.11.5.6 VLAN Miscellaneous Register 5.11.5.7 Spanning Tree Table 5.12 Quality of Service (QOS) 5.12.1 Priority Classification 5.12.1.1 Base Control Register 5.12.1.2 Port Priority Map 5.12.1.3 VLAN Priority Map 5.12.1.4 TOS/DSCP Priority Map 5.12.1.5 TCP/UDP Port Priority 5.12.2 Queue Scheduling Configuration Register 5.13 QoS Multi-Field Classification 5.13.1 Multi-Field Classification Table Control Register 5.13.2 Multi-Field Classification Register 5.13.3 Multi-Field Table QoS Rate Control Register 5.13.4 Multi-Field Access Control Register 5.13.5 Multi-Field Status Register 5.14 Auto Blocking/Recovery loop port 6 Crystal Specifications 7 Electrical Characteristics 7.1 Absolute Maximum Rating 7.2 DC Characteristic 7.3 AC Timing 7.3.1 Power On Sequence and Reset Timing 7.3.2 PHY Mode MII (Turbo MII) Timing 7.3.3 MAC Mode MII (Turbo MII) Timing 7.3.4 RMII Timing 7.3.5 SMI Timing 7.3.6 EEPROM Timing 7.4 Thermal Data 8 Order Information 9 Package Detail 68 QFN Outline Dimensions 9.2 68 QFN PCB footprint
(continued) Pin No. Label Type Description LED pins used as initial setting (the setting is latched at the end of reset)
54 LINK_Q IPH1 Link quality 1: enable (default) 0: disable When the function is enabled, besides link on/off status, activity status, link LED shows link quality. The link LED will be flash (on: 2sec / off: 2sec) when the SNR of received signal is lower than the desired value for normal operation. 9/116 April 11, 2018 Copyright © 2007, IC Plus Corp. IP175LLF-DS-R04 Document Outline Comparison Table between IP175D and IP175LLF 1 Pin Diagram 1.1 IP175LLF Pin diagram (QFN68) 2 Pin Description 3 Function Description 3.1 Flow Control 3.2 Broadcast Storm Protection 3.3 Rate Control 3.4 External MII 3.4.1 To define the speed, duplex and pause of MII port 3.4.2 The Application Circuit of RMII 3.5 Virtual LAN (VLAN) 3.5.1 Port-based VLAN 3.5.2 Tag-based VLAN 3.5.3 VLAN Ingress Filtering 3.5.4 Shared and Independent VLAN Learning 3.5.5 The determination of the requirement to insert or remove tag 3.6 Quality of Service (QoS) 3.6.1 Traffic Policy 3.6.2 Priority Classification 3.6.3 Output Queue Scheduling 3.7 Port mirror 3.8 Layer 2-4 Multi-Field Classification 3.9 MAC Address Table 3.9.1 Entry Content 3.9.2 Accessing MAC Table 3.10 CPU Interrupt Control for loop detection 3.11 IGMP Snooping 3.12 Security Filtering 3.12.1 Physical Port Filtering 3.12.2 MAC Address Filtering 3.12.3 Logical Port Filtering 3.12.4 Layer 2-4 Multi-Field Filtering 3.13 IEEE 802.1x 3.14 Spanning Tree 3.15 Special Tag 3.16 Loop Detection 3.17 LED Blink Timing 3.18 Serial Management Interface 3.19 Reset 3.20 Built in regulator 4 PHY Register 4.1 PHY ID Map 4.2 PHY 0~3 and 5 Register Map 4.3 MII Register 0 4.3.1 MII Register 0 of PHY0~3 4.3.2 MII Register 0 of PHY5 4.4 MII Register 1 4.4.1 MII Register 1 of PHY0~3 4.4.2 MII Register 1 of PHY5 4.5 MII Register 2 of PHY0~3 (4 PHYs share the MII register) 4.6 MII Register 3 of PHY0~3 (4 PHYs share the MII register) 4.7 MII Register 4 4.7.1 MII Register 4 of PHY0~3 4.7.2 MII Register 4 of PHY5 4.8 MII Register 5 4.8.1 MII Register 5 of PHY0~3 4.8.2 MII Register 5 of PHY5 4.9 MII Register 6 of PHY0~3 4.10 MII Register 16 of PHY0~3 (4 PHYs share the MII register) 4.11 MII Register 18 of PHY0~3 4.12 MII Register 22 of PHY0~3 (4 PHYs share the MII register) 5 Switch Register 5.1 Switch Register Map 5.2 Switch Register EEPROM Map 5.3 Switch Control Register 5.3.1 Chip Identification 5.3.2 Software Reset Register 5.3.3 MII Force Mode 5.3.4 Congestion Control Register 5.3.5 Port State 5.3.6 Illegal Frame Filter 5.3.7 Special Packet Identification 5.3.7.1 Reserved Address 01-80-C2-00-00-00 to 01-80-C2-00-00-1F 5.3.7.2 Reserved Address 01-80-C2-00-00-20 to 01-80-C2-00-00-FF 5.3.7.3 Miscellaneous Special Packet Identification 5.3.8 Network Security 5.3.9 Learning Control Register 5.3.10 Aging Time Parameter 5.3.11 Broadcast Storm Protection 5.3.12 Port Mirror 5.3.13 Source Block Protection 5.3.14 LED Control Register 5.4 External MII Control Register 5.4.1 External MII Status Report Register 5.4.2 MII0 MAC Mode Register 5.4.3 MII0 Control Register 1 5.4.4 MII0 Control Register 2 5.5 IGMP Control Register 5.5.1 Base Control Register 5.5.2 Router Port Timeout 5.5.3 IGMP Group Timeout 5.6 Rate Control 5.6.1 Basic Rate Setting Register 5.6.2 Rate Setting Access Control Register 5.7 Address Table Access Register 5.7.1 Command Register 5.7.2 Data Buffer Register (For Unicast MAC Address) 5.7.3 Data Buffer Register (For Multicast MAC Address) 5.7.4 Data Buffer Register (For IP Multicast Address) 5.8 CPU Interrupt Register 5.8.1 CPU Interrupt Control Register 5.8.2 Loop detection enable Register 5.8.3 Loop port indicator Register 5.9 Miscellaneous Control Register 5.10 CRC Counter 5.11 VLAN Group Control Register 5.11.1 VLAN Classification 5.11.2 VLAN Ingress Rule 5.11.3 VLAN Egress Rule 5.11.4 Default VLAN Information 5.11.5 VLAN Table 5.11.5.1 VLAN Control Register 5.11.5.2 VLAN Identifier Register 5.11.5.3 VLAN Member Register 5.11.5.4 Add Tag Control Register 5.11.5.5 Remove Tag Control Register 5.11.5.6 VLAN Miscellaneous Register 5.11.5.7 Spanning Tree Table 5.12 Quality of Service (QOS) 5.12.1 Priority Classification 5.12.1.1 Base Control Register 5.12.1.2 Port Priority Map 5.12.1.3 VLAN Priority Map 5.12.1.4 TOS/DSCP Priority Map 5.12.1.5 TCP/UDP Port Priority 5.12.2 Queue Scheduling Configuration Register 5.13 QoS Multi-Field Classification 5.13.1 Multi-Field Classification Table Control Register 5.13.2 Multi-Field Classification Register 5.13.3 Multi-Field Table QoS Rate Control Register 5.13.4 Multi-Field Access Control Register 5.13.5 Multi-Field Status Register 5.14 Auto Blocking/Recovery loop port 6 Crystal Specifications 7 Electrical Characteristics 7.1 Absolute Maximum Rating 7.2 DC Characteristic 7.3 AC Timing 7.3.1 Power On Sequence and Reset Timing 7.3.2 PHY Mode MII (Turbo MII) Timing 7.3.3 MAC Mode MII (Turbo MII) Timing 7.3.4 RMII Timing 7.3.5 SMI Timing 7.3.6 EEPROM Timing 7.4 Thermal Data 8 Order Information 9 Package Detail 68 QFN Outline Dimensions 9.2 68 QFN PCB footprint