Datasheet SR6P3EC4 (STMicroelectronics) - 2
| 制造商 | STMicroelectronics |
| 描述 | 32-bit Arm Cortex R52+ automotive integration MCU 4 Cortex R52+ cores, 19.5 MB xMemory, 1.8 MB RAM, with embedded virtualization, safety, and security in FPBGA292 package |
| 页数 / 页 | 10 / 2 — SR6P3EC4 SR6P3EC6. Security: 2nd generation hardware security module |
| 文件格式/大小 | PDF / 572 Kb |
| 文件语言 | 英语 |
SR6P3EC4 SR6P3EC6. Security: 2nd generation hardware security module
该数据表的模型线
文件文字版本
link to page 9 link to page 9
SR6P3EC4 SR6P3EC6 Security: 2nd generation hardware security module
• Cybersecurity: ISO/SAE 21434 compliance (refer to the cybersecurity reference manual for details) • On-chip high-performance security module with full support for e-safety vehicle intrusion protected applications (EVITA) • Symmetric and asymmetric cryptography processor • High-performance lock-stepped AES-light security subsystem for fast ASIL-D cryptographic services
Safety: comprehensive new-generation ASIL-D safety concept
• New state-of-the-art safety measures at all levels of the architecture for most efficient implementation of ISO 26262 ASIL-D functionalities • Complete hardware virtualization architecture built on Cortex®‑R52+ new privilege mode (best-in-class software isolation, real-time support for multiple virtual machines/applications)
Device standby/low-power modes
• Versatile low-power modes • Ultra-low power: standby mode for lowest quiescent current with optimized active subsystem (for example standby RAM) and wake-up capability • Smart low-power: smart power mode with Cortex®‑M4 subsystem, extended communications interfaces, and ADC peripheral
Peripheral, I/O, and communication interfaces
• 8 LINFlexD modules • 1 dual-channel FlexRay controller • 10 queued serial peripheral interface (SPIQ) modules • 2 microsecond channels (MSC) • 2 I²C interfaces • 2 SENT modules (10 channels each) • 2 PSI5 modules (1 channel each) • Enhanced analog-to-digital converter system with: – 12 separate 12-bit SAR analog converters (including one supervisor/safety ADC). – 4 separate 9-bit SAR analog converters (2 channels each) with fast comparator mode – 1× 9-bit SAR analog converter for device standby/low-power mode – 10 separate 16-bit sigma-delta analog converters with embedded DSP processor on each SDADC – Enhanced interconnection with GTM timer for autonomous ADC/GTM subsystem operation • Advanced timed I/O capability: – Generic timer module (GTM4134) – High-resolution timer • Communication interfaces: – One 10/100/1000 Mbit/s Ethernet controller compliant with IEEE 802.3-2008: IPv4 and IPv6 checksum modules, AVB, VLAN, and optionally supporting 10BASE-T1S with the OPEN Alliance 3- pin (OA3p) interface (depending on the ordered part number) – 8 modular controller area network (MCAN) modules, supporting CAN classic and CAN FD® – 2 XS_CAN modules supporting CAN classic, CAN FD® and CAN XL®
DB5468
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Rev 4 page 2/10
Document Outline SR6P3EC4 SR6P3EC6 Features 1 Introduction 1.1 Document overview 1.2 Description 1.3 Block diagram 2 Ordering information Revision history Glossary ADC AEC AES ASIL ATOM CAN CAN FD® CAN XL® CPU CRC DCF DMA DSP eDMA EMC EVITA FCCU FPBGA FPU GB GPIO GTM HSM I/O I2C IEC IEEE IPv4 IPv6 ISO JTAG KB LIN LVDS M_TTCAN MB MCAN MCS MCU MII NoC NPU NVM OA3p OS OSR OTA PHY PLL PSI5 RAM RGMII RMII SAR SDADC SENT SIMD SIPI SPI SPIQ SRAM SRC ST SWD TIM TIO TOM UART VLAN xMemory XS_CAN
SR6P3EC4 SR6P3EC6 Security: 2nd generation hardware security module
• Cybersecurity: ISO/SAE 21434 compliance (refer to the cybersecurity reference manual for details) • On-chip high-performance security module with full support for e-safety vehicle intrusion protected applications (EVITA) • Symmetric and asymmetric cryptography processor • High-performance lock-stepped AES-light security subsystem for fast ASIL-D cryptographic services
Safety: comprehensive new-generation ASIL-D safety concept
• New state-of-the-art safety measures at all levels of the architecture for most efficient implementation of ISO 26262 ASIL-D functionalities • Complete hardware virtualization architecture built on Cortex®‑R52+ new privilege mode (best-in-class software isolation, real-time support for multiple virtual machines/applications)
Device standby/low-power modes
• Versatile low-power modes • Ultra-low power: standby mode for lowest quiescent current with optimized active subsystem (for example standby RAM) and wake-up capability • Smart low-power: smart power mode with Cortex®‑M4 subsystem, extended communications interfaces, and ADC peripheral
Peripheral, I/O, and communication interfaces
• 8 LINFlexD modules • 1 dual-channel FlexRay controller • 10 queued serial peripheral interface (SPIQ) modules • 2 microsecond channels (MSC) • 2 I²C interfaces • 2 SENT modules (10 channels each) • 2 PSI5 modules (1 channel each) • Enhanced analog-to-digital converter system with: – 12 separate 12-bit SAR analog converters (including one supervisor/safety ADC). – 4 separate 9-bit SAR analog converters (2 channels each) with fast comparator mode – 1× 9-bit SAR analog converter for device standby/low-power mode – 10 separate 16-bit sigma-delta analog converters with embedded DSP processor on each SDADC – Enhanced interconnection with GTM timer for autonomous ADC/GTM subsystem operation • Advanced timed I/O capability: – Generic timer module (GTM4134) – High-resolution timer • Communication interfaces: – One 10/100/1000 Mbit/s Ethernet controller compliant with IEEE 802.3-2008: IPv4 and IPv6 checksum modules, AVB, VLAN, and optionally supporting 10BASE-T1S with the OPEN Alliance 3- pin (OA3p) interface (depending on the ordered part number) – 8 modular controller area network (MCAN) modules, supporting CAN classic and CAN FD® – 2 XS_CAN modules supporting CAN classic, CAN FD® and CAN XL®
DB5468
-
Rev 4 page 2/10
Document Outline SR6P3EC4 SR6P3EC6 Features 1 Introduction 1.1 Document overview 1.2 Description 1.3 Block diagram 2 Ordering information Revision history Glossary ADC AEC AES ASIL ATOM CAN CAN FD® CAN XL® CPU CRC DCF DMA DSP eDMA EMC EVITA FCCU FPBGA FPU GB GPIO GTM HSM I/O I2C IEC IEEE IPv4 IPv6 ISO JTAG KB LIN LVDS M_TTCAN MB MCAN MCS MCU MII NoC NPU NVM OA3p OS OSR OTA PHY PLL PSI5 RAM RGMII RMII SAR SDADC SENT SIMD SIPI SPI SPIQ SRAM SRC ST SWD TIM TIO TOM UART VLAN xMemory XS_CAN