Datasheet SR6P3EC4 (STMicroelectronics) - 5
| 制造商 | STMicroelectronics |
| 描述 | 32-bit Arm Cortex R52+ automotive integration MCU 4 Cortex R52+ cores, 19.5 MB xMemory, 1.8 MB RAM, with embedded virtualization, safety, and security in FPBGA292 package |
| 页数 / 页 | 10 / 5 — DB5468. 1.3. Block diagram. Rev 4. Figure 1. Block diagram. Safe network … |
| 文件格式/大小 | PDF / 572 Kb |
| 文件语言 | 英语 |
DB5468. 1.3. Block diagram. Rev 4. Figure 1. Block diagram. Safe network on chip with QOS / firewalling. SR6P3EC4 SR6P3EC6
该数据表的模型线
文件文字版本
DB5468 1.3 Block diagram
- The figure below shows the top-level block diagram.
Rev 4 Figure 1. Block diagram
NVM configuration 10 MB 14 MB 19.5 MB Fix configurations SR6P3Exx92x SR6P3Exx96x N/A xMemory configurations SR6P3ExxXMx Memories Connectivity Accelerators ADC & COM accelerator RAM 1792 KB Ethernet(1) 8× CAN FD 8× LIN 1× Cortex®-M4 (1× LS) 1× 1 Gbit/s-100-10 Mbit/s “DSPH” PCM 10 14 15.5 19.5 MB (included 10BASE-T1S) 2× CAN XL / FD 1× FlexRAY 2× PSI5 2× I²C Data PCM 256+128 KB DSPL (on 6× SDADC) 1× LFAST (C2C) 2× SENT (20 ch) 10× SPI (2× with LVDS) Neural Art 11 2× MSC Analog / timers
Safe network on chip with QOS / firewalling
System Analog inputs–98 ch Hardware based SARADC a-comp SDADC embedded Lockstep Split-lock 12× 12 bit 4× 9 bit 10× 16 bit virtualization Cortex®-R52+ Cortex®-R52+ 1× 9 bit LP ADC – 8 ch ASIL-D SEooC 500 MHz 500 MHz GTM4134 I-/D- I-/D- High-resolution timer Standby low-power cache TCM cache TCM 1× 64 bit GST Smart low-power (with DSPH) Lockstep
SR6P3EC4 SR6P3EC6
Security 4× DMA Cortex®-R52+ Cortex®-R52+ 500 MHz 500 MHz HSM 200 MHz 2× CRC (4 ch) 2× AES light 9× SWT I-/D- I-/D- cache TCM cache TCM Lockstep–500 MHz Debug & trace
Introduction
Core local RAMs (per core)
page 5/10
I-/ D- cache 16 KB/8 KB TCM 128 KB 1. 10 Mbit/s Ethernet sharing the same link as 1 Gbit/s-100 Mbit/s Ethernet. The 10BASE-T1S feature is optional (depending on the ordered part number). Document Outline SR6P3EC4 SR6P3EC6 Features 1 Introduction 1.1 Document overview 1.2 Description 1.3 Block diagram 2 Ordering information Revision history Glossary ADC AEC AES ASIL ATOM CAN CAN FD® CAN XL® CPU CRC DCF DMA DSP eDMA EMC EVITA FCCU FPBGA FPU GB GPIO GTM HSM I/O I2C IEC IEEE IPv4 IPv6 ISO JTAG KB LIN LVDS M_TTCAN MB MCAN MCS MCU MII NoC NPU NVM OA3p OS OSR OTA PHY PLL PSI5 RAM RGMII RMII SAR SDADC SENT SIMD SIPI SPI SPIQ SRAM SRC ST SWD TIM TIO TOM UART VLAN xMemory XS_CAN
- The figure below shows the top-level block diagram.
Rev 4 Figure 1. Block diagram
NVM configuration 10 MB 14 MB 19.5 MB Fix configurations SR6P3Exx92x SR6P3Exx96x N/A xMemory configurations SR6P3ExxXMx Memories Connectivity Accelerators ADC & COM accelerator RAM 1792 KB Ethernet(1) 8× CAN FD 8× LIN 1× Cortex®-M4 (1× LS) 1× 1 Gbit/s-100-10 Mbit/s “DSPH” PCM 10 14 15.5 19.5 MB (included 10BASE-T1S) 2× CAN XL / FD 1× FlexRAY 2× PSI5 2× I²C Data PCM 256+128 KB DSPL (on 6× SDADC) 1× LFAST (C2C) 2× SENT (20 ch) 10× SPI (2× with LVDS) Neural Art 11 2× MSC Analog / timers
Safe network on chip with QOS / firewalling
System Analog inputs–98 ch Hardware based SARADC a-comp SDADC embedded Lockstep Split-lock 12× 12 bit 4× 9 bit 10× 16 bit virtualization Cortex®-R52+ Cortex®-R52+ 1× 9 bit LP ADC – 8 ch ASIL-D SEooC 500 MHz 500 MHz GTM4134 I-/D- I-/D- High-resolution timer Standby low-power cache TCM cache TCM 1× 64 bit GST Smart low-power (with DSPH) Lockstep
SR6P3EC4 SR6P3EC6
Security 4× DMA Cortex®-R52+ Cortex®-R52+ 500 MHz 500 MHz HSM 200 MHz 2× CRC (4 ch) 2× AES light 9× SWT I-/D- I-/D- cache TCM cache TCM Lockstep–500 MHz Debug & trace
Introduction
Core local RAMs (per core)
page 5/10
I-/ D- cache 16 KB/8 KB TCM 128 KB 1. 10 Mbit/s Ethernet sharing the same link as 1 Gbit/s-100 Mbit/s Ethernet. The 10BASE-T1S feature is optional (depending on the ordered part number). Document Outline SR6P3EC4 SR6P3EC6 Features 1 Introduction 1.1 Document overview 1.2 Description 1.3 Block diagram 2 Ordering information Revision history Glossary ADC AEC AES ASIL ATOM CAN CAN FD® CAN XL® CPU CRC DCF DMA DSP eDMA EMC EVITA FCCU FPBGA FPU GB GPIO GTM HSM I/O I2C IEC IEEE IPv4 IPv6 ISO JTAG KB LIN LVDS M_TTCAN MB MCAN MCS MCU MII NoC NPU NVM OA3p OS OSR OTA PHY PLL PSI5 RAM RGMII RMII SAR SDADC SENT SIMD SIPI SPI SPIQ SRAM SRC ST SWD TIM TIO TOM UART VLAN xMemory XS_CAN