Datasheet MAX5048 (Analog Devices) - 7

MAX5048 7.6A, 12ns, SOT23/TDFN, MOSFET Driver Pin Description Undervoltage Lockout (UVLO)
When V+ is below the UVLO threshold, the N-channel
PIN NAME FUNCTION
is ON and the P-channel is OFF, independent of the Power Supply. Bypass to GND with a state of the inputs. The UVLO is typically 3.6V with 1 V+ 0.1µF ceramic capacitor. 400mV typical hysteresis to avoid chattering. p-Channel Open-Drain Output. Sources
Driver Outputs
2 P_OUT current for MOSFET turn-on. The MAX5048A/MAX5048B provide two separate out- puts. One is an open-drain P-channel, the other an n-Channel Open-Drain Output. Sinks 3 N_OUT open-drain N-channel. They have distinct current sourc- current for MOSFET turn-off. ing/sinking capabilities to independently control the rise 4 GND Ground and fall times of the MOSFET gate. Add a resistor in Inverting Logic Input Terminal. Connect series with P_OUT/N_OUT to slow the corresponding 5 IN- to GND when not used. rise/fall time of the MOSFET gate. Noninverting Logic Input Terminal.
Applications Information
6 IN+ Connect to V+ when not used.
Supply Bypassing, Device Grounding,
Exposed paddle. Connect to GND.
and Placement
— EP Solder EP to the GND plane for Ample supply bypassing and device grounding are improved thermal performance. extremely important because when large external capacitive loads are driven, the peak current at the V+
Detailed Description
pin can approach 1.3A, while at the GND pin the peak
Logic Inputs
current can approach 7.6A. VCC drops and ground The MAX5048A/MAX5048Bs’ logic inputs are protected shifts are forms of negative feedback for inverters and, if against voltage spikes up to +14V, regardless of the V+ excessive, can cause multiple switching when the IN- voltage. The low 2.5pF input capacitance of the inputs input is used and the input slew rate is low. The device reduces loading and increases switching speed. These driving the input should be referenced to the devices have two inputs that give the user greater flexi- MAX5048A/MAX5048B GND pin especially when the IN- bility in controlling the MOSFET. Table 1 shows all pos- input is used. Ground shifts due to insufficient device sible input combinations. grounding may disturb other circuits sharing the same AC ground return path. Any series inductance in the V+, The difference between the MAX5048A and the P_OUT, N_OUT and/or GND paths can cause oscilla- MAX5048B is the input threshold voltage. The tions due to the very high di/dt that results when the MAX5048A has VCC/2 CMOS logic-level thresholds, MAX5048A/MAX5048B are switched with any capacitive while the MAX5048B has TTL logic-level thresholds (see load. A 0.1µF or larger value ceramic capacitor is rec- the Electrical Characteristics). For V+ above 5.5V, VIH ommended bypassing V+ to GND and placed as close (typ) = 0.5x(V+) + 0.8V and VIL (typ) = 0.5x(V+) - 0.8V. to the pins as possible. When driving very large loads As V+ is reduced from 5.5V to 4V, VIH and VIL gradually (e.g., 10nF) at minimum rise time, 10µF or more of paral- approach VIH (typ) = 0.5x(V+) + 0.65V and VIL (typ) = lel storage capacitance is recommended. A ground 0.5x(V+) - 0.65V. Connect IN+ to V+ or IN- to GND plane is highly recommended to minimize ground return when not used. Alternatively, the unused input can be resistance and series inductance. Care should be taken used as an ON/OFF pin (see Table 1). to place the MAX5048A/MAX5048B as close as possi- ble to the external MOSFET being driven to further mini-
Table 1. Truth Table
mize board inductance and AC path resistance.
IN+ IN- p-CHANNEL n-CHANNEL Power Dissipation
L L OFF ON Power dissipation of the MAX5048A/MAX5048B con- sists of three components, caused by the quiescent L H OFF ON current, capacitive charge and discharge of internal H L ON OFF nodes, and the output current (either capacitive or H H OFF ON resistive load). The sum of these components must be L = Logic low kept below the maximum power-dissipation limit. H = Logic high Maxim Integrated 7