Datasheet RA6W1 (Renesas) - 10

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RA6W1 Datasheet
Table 50: SD/eMMC host timing parameters .. 99 Table 51: SD/eMMC pin configuration ... 100 Table 52: OQSPI pin configuration .. 101 Table 53: QSPI pin configuration ... 105 Table 54: Timer features overview .. 110 Table 55: Pin function list ... 111 Table 56: Pin configuration .. 114 Table 57: ADC DC specification .. 115 Table 58: ADC pin configuration .. 116 Table 59: Bluetooth coexistence priority example ... 117 Table 60: RA6W1 use cases ... 120 Table 61: Register map APU_AUD ... 128 Table 62: APU_DMIC_CTRL_REG (0x400E0400) ... 128 Table 63: APU_DMIC_DIV_REG (0x400E040C) .. 128 Table 64: APU_MAIN_DIV_REG (0x400E0424) ... 129 Table 65: APU_SYNC_DIV_SEL_REG (0x400E0428) ... 129 Table 66: APU_SYNC_DIV_REG (0x400E042C) ... 130 Table 67: Register map APU_DSP ... 130 Table 68: APU_CTRL_REG (0x400E0800) .. 130 Table 69: APU_MUX_CTRL_REG (0x400E0804) .. 130 Table 70: APU_SYNC_SRC1IN_SEL_REG (0x400E0808) .. 131 Table 71: APU_SYNC_SRC1OUT_SEL_REG (0x400E0810) .. 131 Table 72: APU_PCM_CLK_REG (0x400E0820) ... 131 Table 73: APU_PCM1_DIV_REG (0x400E0824) .. 132 Table 74: Register map CACHE .. 132 Table 75: CACHE_CTRL2_REG (0x0E010020) ... 132 Table 76: CACHE_MRM_HITS_REG (0x0E010028) .. 134 Table 77: CACHE_MRM_MISSES_REG (0x0E01002C) .. 134 Table 78: CACHE_MRM_CTRL_REG (0x0E010030) .. 134 Table 79: CACHE_MRM_TINT_REG (0x0E010034) .. 135 Table 80: CACHE_MRM_MISSES_THRES_REG (0x0E010038) .. 135 Table 81: CACHE_MRM_HITS_THRES_REG (0x0E01003C) ... 135 Table 82: CACHE_FLASH_REG (0x0E010040) ... 135 Table 83: CACHE_MRM_HITS1WS_REG (0x0E010048) .. 136 Table 84: SWD_RESET_REG (0x0E010050) ... 136 Table 85: Register map CRG .. 137 Table 86: RETAIN_MEM_CTRL_REG (0x400C001C) ... 137 Table 87: RESET_STAT_REG (0x400C0024) .. 137 Table 88: PMU_CTRL_REG (0x400C0028) .. 138 Table 89: Register map CRG_APU ... 138 Table 90: APU_AUD_CLK_REG (0x400E0000) ... 138 Table 91: APU_SRC_CLK_REG (0x400E0004) ... 139 Table 92: AUD_CLK_GATE_REG (0x400E000C) .. 140 Table 93: APU_MCLK_CTRL_REG (0x400E0010) .. 141 Table 94: APU_START_CTRL_REG (0x400E0014) .. 141 Table 95: Register map crg_preg_common_3095_01 .. 141 Table 96: XTAL40M_CTRL_REG (0x400C0204) .. 142 Table 97: MEMORY_CTRL_REG (0x400C0208) ... 143 R19DS0136EK0100 Rev. 1.00 Page 10 Nov 26, 2025 CFR0011-120-00 Document Outline Features Applications Contents Figures Tables 1. Terms and Definitions 2. Block Diagrams 3. Part Numbering 4. RA6W1 Product Group 5. Pin Information 5.1 FCQFN Pinout 5.2 WLCSP Pinout 5.3 Pin Descriptions 6. Specifications 6.1 Absolute Maximum Ratings 6.2 Recommended Operating Conditions 6.3 DC Characteristics 6.4 Crystal Oscillator 40 MHz – Recommended Operating Conditions 6.5 XTAL32K – Recommended Operating Conditions 6.6 GPADC – DC Characteristics 6.7 GPADC – Electrical Performance 6.8 RST_N Digital I/O – Recommended Operating Conditions 6.9 GPIO – Recommended Operating Conditions 6.10 GPIO – DC Characteristics 6.11 Radio 6.11.1 wlCSP Package WLAN Radio Characteristics 6.11.2 QFN Package WLAN Radio Characteristics 7. System Overview 8. Core System 8.1 Arm Cortex-M33 8.1.1 Introduction 8.1.2 Interrupts 8.1.3 Debug 8.2 Internal Memory Architecture 8.2.1 Introduction 8.2.2 ROM 8.2.3 System RAM 8.2.4 Retention RAM 8.2.5 OTP 8.2.6 System Address Map 8.3 Clock Generation 8.3.1 Introduction 8.3.2 System Clock (SYS_CLK, HCLK) 8.3.3 Peripheral Clocks (SPI_CLK, PERI_CLK, AUX_CLK) 8.3.4 Audio Clocks (AUD_CLK) 8.3.5 RTC Clocks (32 kHz) 8.4 Power Management 8.4.1 Power-On Sequence 8.4.2 Power Management Unit 8.5 Sleep Modes 8.5.1 Introduction 8.5.2 Wake-Up Sources 8.5.3 Sleep Mode Active Blocks Overview 8.6 DMA 8.6.1 Introduction 8.6.2 General Purpose DMA 8.6.2.1 Input/Output Multiplexer 8.6.2.2 DMA Channel Operation 8.6.2.3 DMA Arbitration 8.6.2.4 Freezing DMA Channels 8.6.3 Fast DMA 8.7 Hardware Accelerators 8.7.1 CRC Calculation 8.7.2 Pseudo Random Number Generation 8.8 Watchdog Timer 8.8.1 Introduction 8.9 Brownout and Blackout Detection 8.10 Security Features 8.10.1 Crypto Engine 8.11 Debug Support 9. Peripherals 9.1 UART 9.1.1 Introduction 9.1.2 RS-232 9.1.3 RS-485 9.1.4 Baud Rate 9.1.5 Hardware Flow Control 9.1.6 Interrupts 9.1.7 DMA Interface 9.1.8 Pin Configuration 9.2 I2C Interface 9.2.1 Introduction 9.2.2 I2C Behavior 9.2.2.1 START and STOP Generation 9.2.2.2 Combined Formats 9.2.3 I2C Protocols 9.2.3.1 START and STOP Conditions 9.2.3.2 Addressing Slave Protocol 9.2.3.2.1 7-bit Address Format 9.2.3.2.2 10-bit Address Format 9.2.3.3 Transmitting and Receiving Protocols 9.2.3.3.1 Master-Transmitter and Slave-Receiver 9.2.3.3.2 Master-Receiver and Slave-Transmitter 9.2.3.3.3 START Byte Transfer Protocol 9.2.4 Multiple Master Arbitration 9.2.5 Clock Synchronization 9.3 Digital Audio Interface (I2S and PDM) 9.3.1 Introduction 9.3.2 Interface Signals 9.3.3 Master and Slave Modes 9.3.4 DAI Slots 9.3.5 DAI Slot Formats 9.3.5.1 I2S Format 9.3.5.2 DSP Format 9.3.5.3 Left-Justified Format 9.3.5.4 Right-Justified Format 9.3.5.5 Time Division Multiplexing Mode 9.3.6 DAI Slot Assignment 9.3.7 DAI PCM_CLK Generation 9.4 SPI Master/Slave 9.4.1 Introduction 9.4.2 SPI Timing 9.5 SDIO 9.5.1 Introduction 9.6 SD/eMMC Host Controller 9.6.1 Introduction 9.7 Octa/Quad SPI Flash Controller – With Secure XIP 9.7.1 Introduction 9.7.1.1 Interface 9.7.1.2 SPI Modes 9.7.1.3 Access Modes 9.7.1.3.1 Auto Mode 9.7.1.3.2 Manual Mode 9.7.1.4 Endianness 9.7.1.5 Erase Suspend/Resume 9.7.1.6 On-the-fly Decryption 9.8 Quad SPI RAM/Flash Controller – PSRAM 9.8.1 Introduction 9.8.2 Interface 9.8.3 SPI Modes 9.8.4 Access Modes 9.8.4.1 Auto Mode Flash Access 9.8.4.2 Auto Mode RAM Access 9.8.4.3 Manual Mode 9.8.5 Endianness 9.8.6 Erase Suspend/Resume 9.8.7 Low Power Considerations 9.9 General Purpose Timers/PWMs 9.9.1 Introduction 9.9.2 Timer Modes of Operation 9.9.2.1 Free-Running Counter 9.9.2.2 PWM Generation 9.9.2.3 Event Capturing 9.9.2.4 One Shot 9.9.2.5 GPIO Pulse Counter 9.9.3 Pin Configuration 9.10 GPIOs and Programmable Pin Assignment 9.11 ADC/Analog or ADC (Aux 12-bit) 9.11.1 Introduction 9.11.2 Timing Diagram 9.11.3 DMA Transfer 9.11.4 Sensor Wake-up 9.11.5 ADC Pin Configuration 9.12 Bluetooth LE/Zigbee Coexistence 9.12.1 One External Radio Coexistence Interface 9.12.2 Two External Radios Coexistence Interface 9.13 Antenna Switching Diversity 9.13.1 Introduction 10. Application Information 10.1 Wi-Fi Application 10.1.1 Typical Wi-Fi Application – FCQFN 10.1.2 Typical Wi-Fi Application – WLCSP 10.1.3 Wi-Fi Application with FEM – FCQFN 10.1.4 Wi-Fi Application with FEM – WLCSP 10.2 Wi-Fi and Bluetooth Combo Application 10.2.1 Typical Wi-Fi and Bluetooth Combo Application – FCQFN 10.2.2 Typical Wi-Fi and Bluetooth Combo Application – WLCSP 10.2.3 Wi-Fi and Bluetooth Combo Application with FEM – FCQFN 10.2.4 Wi-Fi and Bluetooth Combo Application with FEM – WLCSP 11. Registers 11.1 APU Registers 11.2 CACHE Registers 11.3 CRG Registers 11.4 CRG APU Registers 11.5 CRG PREG Registers 11.6 DAI Registers 11.7 DCACHE Registers 11.8 DMA Registers 11.9 GPIO Registers 11.10 General Purpose System Status Registers 11.11 I2C Registers 11.12 KDMA Registers 11.13 MEMCTRL Registers 11.14 OQSPI Registers 11.15 QSPI Registers 11.16 Retention Memory Control Registers 11.17 RTC Registers 11.18 SD/EMMC Registers 11.19 SDIO Registers 11.20 SPI Registers 11.21 SPI2 Registers 11.22 Source FIFO Registers 11.23 Source Interface Registers 11.24 Watchdog Timer Control Registers 11.25 AHB DMA Registers 11.26 AHB Arbitration Registers 11.27 Timer6 Registers 11.28 Timer Control Registers 11.29 Timer2 Control Registers 11.30 Timer3 Control Registers 11.31 Timer4 Control Registers 11.32 Timer5 Control Registers 11.33 Timer7 Control Registers 11.34 Timer8 Control Registers 11.35 UART Registers 11.36 UART2 Registers 11.37 ID Registers 12. Package Information 12.1 Moisture Sensitivity Level (MSL) 12.2 WLCSP Handling 12.3 Soldering Information 12.4 Package Outline Drawings 13. Revision History Appendix A ECAD Design Information A.1 Part Number Indexing A.2 Symbol Pin Information A.2.1 66-QFN A.2.2 70-WLCSP A.3 Symbol Parameters A.4 Footprint Design Information A.4.1 66-QFN A.4.2 70-WLCSP