Datasheet PAC1711 (Microchip) - 7
| 制造商 | Microchip |
| 描述 | 42V Power Monitor with I2C and Alert, 12--bit |
| 页数 / 页 | 91 / 7 — PAC1711. 2.0. TYPICAL PERFORMANCE CURVES. Note:. T = +25°C. = 2.7V. ▬ T = … |
| 文件格式/大小 | PDF / 2.0 Mb |
| 文件语言 | 英语 |
PAC1711. 2.0. TYPICAL PERFORMANCE CURVES. Note:. T = +25°C. = 2.7V. ▬ T = -40°C. ▬ T = 0°C. ▬ T = +25°C. ▬ T = +85°C. ▬ T = +125°C
该数据表的模型线
文件文字版本
PAC1711 2.0 TYPICAL PERFORMANCE CURVES Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise indicated, TA = -40°C to +125°C, VDD = 2.7V to 5.5V, VBUS = 0V to 42V, VSENSE = VSENSE+ – VSENSE– = 0V. 5 0.002
T = +25°C V = 2.7V DD ▬ T = -40°C A A
0.0015
▬ T = 0°C
0
A ▬ T = +25°C A ▬ T = +85°C
0.001
A ▬ T = +125°C
-5
A
0.0005 -10
of Full Scale) of Full Scale)
0 -15 -0.0005
Error (% Error (%
-20 -0.001
▬ V = 2.7V DD ▬ V = 5.5V DD SENSE SENSE
-25
V
-0.0015
V
-30 -0.002 0.00001 0.0001 0.001 0.01 0.1 -0.1 -0.075 -0.05 -0.025 0 0.025 0.05 0.075 0.1
V (V) V (V) SENSE SENSE FIGURE 2-1:
VSENSE Error vs. VSENSE,
FIGURE 2-4:
VSENSE Error vs. VSENSE, TA = 25°C, Multiple VDD, Unipolar Mode. VDD = 2.7V, Multiple TA, Bipolar FSR Mode. 0.0004 0.003
T = +25°C ▬ T = -40°C A ▬ V = 2.7V V = 5.5V A DD
0.0003
DD ▬ V = 5.5V ▬ T = 0°C DD
0.002
A ▬ T = +25°C A
0.0002
▬ T = +85°C A
0.001
▬ T = +125°C A
0.0001 0 0
of Full Scale) of Full Scale)
-0.0001 -0.001 -0.0002 -0.002
Error (%
-0.0003
Error (%
-0.003 -0.0004
SENSE SENSE V
-0.004 -0.0005
V
-0.0006 -0.005 -0.1 -0.075 -0.05 -0.025 0 0.025 0.05 0.075 0.1 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
V (V) V (V) SENSE SENSE FIGURE 2-2:
VSENSE Error vs. VSENSE,
FIGURE 2-5:
VSENSE Error vs. VSENSE, TA = 25°C, Multiple VDD, Bipolar FSR Mode. VDD = 5.5V, Multiple TA, Unipolar Mode. 0.0025 0.003
V = 5.5V ▬ T = -40°C DD A V = 2.7V DD ▬ T = -40°C
0.002
▬ T = 0°C A A ▬ T = 0°C ▬ T = +25°C
0.002
A A ▬ T = +25°C
0.0015
▬ T = +85°C A A ▬ T = +85°C ▬ T = +125°C A A ▬ T = +125°C
0.001 0.001
A
0.0005 0
of Full Scale) of Full Scale)
0 -0.001 -0.0005
Error (%
-0.001
Error (%
-0.002 -0.0015
SENSE SENSE
-0.003
V
-0.002
V
-0.0025 -0.004 -0.1 -0.075 -0.05 -0.025 0 0.025 0.05 0.075 0.1 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
V (V) V (V) SENSE SENSE FIGURE 2-3:
VSENSE Error vs. VSENSE,
FIGURE 2-6:
VSENSE Error vs. VSENSE, VDD = 5.5V, Multiple TA, Bipolar FSR Mode. VDD = 2.7V, Multiple TA, Unipolar Mode. 2025 Microchip Technology Inc. and its subsidiaries DS20007058A-page 7 Document Outline Single-Channel Power Monitor with Accumulator, 42V Full Scale Range Features Applications Description Package Types Functional Block Diagram 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings (†) FIGURE 1-1: PAC1711 ESD Protection Circuitry. 1.2 DC Electrical Specifications 1.3 AC Electrical Specifications 1.4 Temperature Specifications 2.0 Typical Performance Curves FIGURE 2-1: VSENSE Error vs. VSENSE, TA = 25°C, Multiple VDD, Unipolar Mode. FIGURE 2-2: VSENSE Error vs. VSENSE, TA = 25°C, Multiple VDD, Bipolar FSR Mode. FIGURE 2-3: VSENSE Error vs. VSENSE, VDD = 5.5V, Multiple TA, Bipolar FSR Mode. FIGURE 2-4: VSENSE Error vs. VSENSE, VDD = 2.7V, Multiple TA, Bipolar FSR Mode. FIGURE 2-5: VSENSE Error vs. VSENSE, VDD = 5.5V, Multiple TA, Unipolar Mode. FIGURE 2-6: VSENSE Error vs. VSENSE, VDD = 2.7V, Multiple TA, Unipolar Mode. FIGURE 2-7: VSENSE Error vs. VSENSE, VDD = 5.5V, Multiple TA, Unipolar Mode, Logarithmic Scale. FIGURE 2-8: VSENSE Error vs. VSENSE, VDD = 2.7V, Multiple TA, Unipolar Mode, Logarithmic Scale. FIGURE 2-9: VSENSE Error vs. VSENSE, VDD = 5.5V, Multiple TA, Bipolar FSR Mode, Zoom View. FIGURE 2-10: VSENSE Error vs. VSENSE, VDD = 2.7V, Multiple TA, Bipolar FSR Mode, Zoom View. FIGURE 2-11: VBUS Error vs. VBUS, TA = 25°C, Multiple VDD, Unipolar Mode, Logarithmic Scale. FIGURE 2-12: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Unipolar Mode, Logarithmic Scale. FIGURE 2-13: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Unipolar Mode, Logarithmic Scale, Zoom View. FIGURE 2-14: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Bipolar FSR Mode. FIGURE 2-15: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Bipolar FSR Mode, Zoom View. FIGURE 2-16: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Bipolar FSR Mode. FIGURE 2-17: VSENSE Zero Input Histogram, Bipolar FSR/2 Mode (n = 10,000 total samples, 8x average). FIGURE 2-18: VBUS Zero Input Histogram, Bipolar FSR/2 Mode (n = 28,000 total samples, 8x average). FIGURE 2-19: VBUS Offset vs. TA, VDD = 3.3V, Bipolar FSR Mode. FIGURE 2-20: VSENSE DC Offset vs. TA, VBUS = 10.5V, Bipolar FSR Mode. FIGURE 2-21: IDD at 1,024 sps vs. TA, Multiple VDD. FIGURE 2-22: IDD in Slow Mode vs. TA, Multiple VDD. FIGURE 2-23: IDD at 8,192 sps vs. TA, Multiple VDD. FIGURE 2-24: IDD vs. TA, Multiple VDD, Multiple Sample Rates. FIGURE 2-25: IDD in Sleep Mode vs. TA, Multiple VDD. FIGURE 2-26: IDD in Power-down Mode vs. TA, Multiple VDD. FIGURE 2-27: ISENSE- vs. TA, Common Mode, Multiple VBUS. FIGURE 2-28: ISENSE+ vs. TA, Common Mode, Multiple VBUS. FIGURE 2-29: VSENSE- Leakage vs. TA, Common Mode, Multiple VBUS. FIGURE 2-30: VSENSE+ Leakage vs. TA, Common Mode, Multiple VBUS. FIGURE 2-31: IOL vs. VOL, TA = 25°C, VDD = 5.5V. FIGURE 2-32: Sample Rate (ƒS) Error across TA = -40°C to +125°C, n = 30,852 Total Samples. FIGURE 2-33: Sample Rate (ƒS) Error across TA = 30°C, n = 10,308 Total Samples. FIGURE 2-34: POR Threshold vs. TA. 3.0 Pin Descriptions TABLE 3-1: PAC1711 Pin Descriptions 3.1 Sense Voltage Pins (VSENSE+ and VSENSE–) 3.2 Ground Pin (GND) 3.3 Positive Power Supply Voltage Pin (VDD) 3.4 SMBus Data (SMBDAT) Pin (SDA) 3.5 SMBus Clock (SMBCLK) Pin (SCL) 3.6 A0 and A1 Multi-functional Pins 3.7 Power-down Pin (PWRDN) 3.8 Positive Bus Voltage Pin (VBUS+) 4.0 Device Description 4.1 Definitions 4.2 Detailed Description 4.3 Voltage Measurement EQUATION 4-1: 4.4 Current Measurement 4.5 Selecting RSHUNT Values EQUATION 4-2: EQUATION 4-3: EQUATION 4-4: 4.6 FSR/2 Modes TABLE 4-1: FSR/2 – VBUS TABLE 4-2: FSR/2 – VSENSE 4.7 ADC Measurements, Offset and Averaging 4.8 Power and Energy EQUATION 4-5: EQUATION 4-6: EQUATION 4-7: EQUATION 4-8: 4.9 Conversion Cycles 4.10 Alert Functionality 5.0 SMBus and I2C Communications Protocols FIGURE 5-1: SMBus Timing Diagram. 5.1 Addressing and Control Bits TABLE 5-1: Address Select 5.2 SMBus Timeout 5.3 SMBus and I2C Compatibility 5.4 SMBus and I2C Standard Protocol TABLE 5-2: Protocol Packet 5.5 Auto-incrementing Pointer FIGURE 5-2: READ and WRITE Auto-incrementing Loops. 5.6 SMBus/I2C Commands TABLE 5-3: Refresh and Refresh_V Commands TABLE 5-4: General Call Response TABLE 5-5: Write Byte TABLE 5-6: Read Byte TABLE 5-7: Send Byte TABLE 5-8: Receive Byte TABLE 5-9: Block Write – I2C version TABLE 5-10: Block Read – I2C Version TABLE 5-11: Block Read – SMBus Version (Must set BYTE COUNT bit) 6.0 Register Description TABLE 6-1: PAC1711 Registers 6.1 Reading Data Bytes 6.2 Register Categories 6.3 Detailed Register Information Register 6-1: REFRESH (Address 00h) FIGURE 6-1: Host Read Period After a Refresh Command. Register 6-2: CONTROL (Address 01h) Register 6-3: ACC_COUNT (Address 02h) Register 6-4: VACC (Address 03h) Register 6-5: VBUS (Address 04h) Register 6-6: VSENSE (Address 05h) Register 6-7: VBUS_AVG (Address 06h) Register 6-8: VSENSE_AVG (Address 07h) Register 6-9: VPOWER (Address 08h) Register 6-10: VBUS_MIN (Address 09h) Register 6-11: VBUS_MAX (Address 0Ah) Register 6-12: VSENSE_MIN (Address 0Bh) Register 6-13: VSENSE_MAX (Address 0Ch) Register 6-14: VPOWER_MIN (Address 0Dh) Register 6-15: VPOWER_MAX (Address 0Eh) Register 6-16: CONTROL_LAT (Address 0Fh) Register 6-17: NEG_PWR_FSR_LAT (Address 10h) Register 6-18: ALERT_STATUS (Address 11h) Register 6-19: SMBUS_SETTINGS (Address 12h) Register 6-20: NEG_PWR_FSR (Address 13h) Register 6-21: REFRESH_G (Address 14h) Register 6-22: REFRESH_V (Address 15h) Register 6-23: SLOW (Address 16h) Register 6-24: CONTROL_ACT (Address 17h) Register 6-25: NEG_PWR_FSR_ACT (Address 18h) Register 6-26: SLOW_ALERT0 (Address 19h) Register 6-27: GPIO_ALERT1 (Address 1Ah) Register 6-28: ACC_FULL_LIMIT (Address 1BH) Register 6-29: OC_LIMIT (Address 1CH) Register 6-30: UC_LIMIT (Address 1DH) Register 6-31: OP_WARNING_LIMIT (Address 1EH) Register 6-32: OP_CRITICAL_LIMIT (Address 1FH) Register 6-33: OV_LIMIT (Address 20H) Register 6-34: UV_LIMIT (Address 21H) Register 6-35: STEP_LIMIT (Address 22H) Register 6-36: N-SAMPLES_LIMIT (Address 23h) Register 6-37: ALERT_ENABLE (Address 24h) Register 6-38: ACC_COUNT_PRESET (Address 25h) Register 6-39: VACC_PRESET (Address 26h) Register 6-40: PRODUCT_ID (Address FDh) Register 6-41: MANUFACTURER_ID (Address FEh) Register 6-42: REVISION_ID (Address FFh) 7.0 Packaging Information 7.1 Package Marking Information 7.2 Package Drawings Appendix A: Revision History Revision A (October 2025) Product Identification System Microchip Information Trademarks Legal Notice Microchip Devices Code Protection Feature
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise indicated, TA = -40°C to +125°C, VDD = 2.7V to 5.5V, VBUS = 0V to 42V, VSENSE = VSENSE+ – VSENSE– = 0V. 5 0.002
T = +25°C V = 2.7V DD ▬ T = -40°C A A
0.0015
▬ T = 0°C
0
A ▬ T = +25°C A ▬ T = +85°C
0.001
A ▬ T = +125°C
-5
A
0.0005 -10
of Full Scale) of Full Scale)
0 -15 -0.0005
Error (% Error (%
-20 -0.001
▬ V = 2.7V DD ▬ V = 5.5V DD SENSE SENSE
-25
V
-0.0015
V
-30 -0.002 0.00001 0.0001 0.001 0.01 0.1 -0.1 -0.075 -0.05 -0.025 0 0.025 0.05 0.075 0.1
V (V) V (V) SENSE SENSE FIGURE 2-1:
VSENSE Error vs. VSENSE,
FIGURE 2-4:
VSENSE Error vs. VSENSE, TA = 25°C, Multiple VDD, Unipolar Mode. VDD = 2.7V, Multiple TA, Bipolar FSR Mode. 0.0004 0.003
T = +25°C ▬ T = -40°C A ▬ V = 2.7V V = 5.5V A DD
0.0003
DD ▬ V = 5.5V ▬ T = 0°C DD
0.002
A ▬ T = +25°C A
0.0002
▬ T = +85°C A
0.001
▬ T = +125°C A
0.0001 0 0
of Full Scale) of Full Scale)
-0.0001 -0.001 -0.0002 -0.002
Error (%
-0.0003
Error (%
-0.003 -0.0004
SENSE SENSE V
-0.004 -0.0005
V
-0.0006 -0.005 -0.1 -0.075 -0.05 -0.025 0 0.025 0.05 0.075 0.1 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
V (V) V (V) SENSE SENSE FIGURE 2-2:
VSENSE Error vs. VSENSE,
FIGURE 2-5:
VSENSE Error vs. VSENSE, TA = 25°C, Multiple VDD, Bipolar FSR Mode. VDD = 5.5V, Multiple TA, Unipolar Mode. 0.0025 0.003
V = 5.5V ▬ T = -40°C DD A V = 2.7V DD ▬ T = -40°C
0.002
▬ T = 0°C A A ▬ T = 0°C ▬ T = +25°C
0.002
A A ▬ T = +25°C
0.0015
▬ T = +85°C A A ▬ T = +85°C ▬ T = +125°C A A ▬ T = +125°C
0.001 0.001
A
0.0005 0
of Full Scale) of Full Scale)
0 -0.001 -0.0005
Error (%
-0.001
Error (%
-0.002 -0.0015
SENSE SENSE
-0.003
V
-0.002
V
-0.0025 -0.004 -0.1 -0.075 -0.05 -0.025 0 0.025 0.05 0.075 0.1 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
V (V) V (V) SENSE SENSE FIGURE 2-3:
VSENSE Error vs. VSENSE,
FIGURE 2-6:
VSENSE Error vs. VSENSE, VDD = 5.5V, Multiple TA, Bipolar FSR Mode. VDD = 2.7V, Multiple TA, Unipolar Mode. 2025 Microchip Technology Inc. and its subsidiaries DS20007058A-page 7 Document Outline Single-Channel Power Monitor with Accumulator, 42V Full Scale Range Features Applications Description Package Types Functional Block Diagram 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings (†) FIGURE 1-1: PAC1711 ESD Protection Circuitry. 1.2 DC Electrical Specifications 1.3 AC Electrical Specifications 1.4 Temperature Specifications 2.0 Typical Performance Curves FIGURE 2-1: VSENSE Error vs. VSENSE, TA = 25°C, Multiple VDD, Unipolar Mode. FIGURE 2-2: VSENSE Error vs. VSENSE, TA = 25°C, Multiple VDD, Bipolar FSR Mode. FIGURE 2-3: VSENSE Error vs. VSENSE, VDD = 5.5V, Multiple TA, Bipolar FSR Mode. FIGURE 2-4: VSENSE Error vs. VSENSE, VDD = 2.7V, Multiple TA, Bipolar FSR Mode. FIGURE 2-5: VSENSE Error vs. VSENSE, VDD = 5.5V, Multiple TA, Unipolar Mode. FIGURE 2-6: VSENSE Error vs. VSENSE, VDD = 2.7V, Multiple TA, Unipolar Mode. FIGURE 2-7: VSENSE Error vs. VSENSE, VDD = 5.5V, Multiple TA, Unipolar Mode, Logarithmic Scale. FIGURE 2-8: VSENSE Error vs. VSENSE, VDD = 2.7V, Multiple TA, Unipolar Mode, Logarithmic Scale. FIGURE 2-9: VSENSE Error vs. VSENSE, VDD = 5.5V, Multiple TA, Bipolar FSR Mode, Zoom View. FIGURE 2-10: VSENSE Error vs. VSENSE, VDD = 2.7V, Multiple TA, Bipolar FSR Mode, Zoom View. FIGURE 2-11: VBUS Error vs. VBUS, TA = 25°C, Multiple VDD, Unipolar Mode, Logarithmic Scale. FIGURE 2-12: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Unipolar Mode, Logarithmic Scale. FIGURE 2-13: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Unipolar Mode, Logarithmic Scale, Zoom View. FIGURE 2-14: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Bipolar FSR Mode. FIGURE 2-15: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Bipolar FSR Mode, Zoom View. FIGURE 2-16: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Bipolar FSR Mode. FIGURE 2-17: VSENSE Zero Input Histogram, Bipolar FSR/2 Mode (n = 10,000 total samples, 8x average). FIGURE 2-18: VBUS Zero Input Histogram, Bipolar FSR/2 Mode (n = 28,000 total samples, 8x average). FIGURE 2-19: VBUS Offset vs. TA, VDD = 3.3V, Bipolar FSR Mode. FIGURE 2-20: VSENSE DC Offset vs. TA, VBUS = 10.5V, Bipolar FSR Mode. FIGURE 2-21: IDD at 1,024 sps vs. TA, Multiple VDD. FIGURE 2-22: IDD in Slow Mode vs. TA, Multiple VDD. FIGURE 2-23: IDD at 8,192 sps vs. TA, Multiple VDD. FIGURE 2-24: IDD vs. TA, Multiple VDD, Multiple Sample Rates. FIGURE 2-25: IDD in Sleep Mode vs. TA, Multiple VDD. FIGURE 2-26: IDD in Power-down Mode vs. TA, Multiple VDD. FIGURE 2-27: ISENSE- vs. TA, Common Mode, Multiple VBUS. FIGURE 2-28: ISENSE+ vs. TA, Common Mode, Multiple VBUS. FIGURE 2-29: VSENSE- Leakage vs. TA, Common Mode, Multiple VBUS. FIGURE 2-30: VSENSE+ Leakage vs. TA, Common Mode, Multiple VBUS. FIGURE 2-31: IOL vs. VOL, TA = 25°C, VDD = 5.5V. FIGURE 2-32: Sample Rate (ƒS) Error across TA = -40°C to +125°C, n = 30,852 Total Samples. FIGURE 2-33: Sample Rate (ƒS) Error across TA = 30°C, n = 10,308 Total Samples. FIGURE 2-34: POR Threshold vs. TA. 3.0 Pin Descriptions TABLE 3-1: PAC1711 Pin Descriptions 3.1 Sense Voltage Pins (VSENSE+ and VSENSE–) 3.2 Ground Pin (GND) 3.3 Positive Power Supply Voltage Pin (VDD) 3.4 SMBus Data (SMBDAT) Pin (SDA) 3.5 SMBus Clock (SMBCLK) Pin (SCL) 3.6 A0 and A1 Multi-functional Pins 3.7 Power-down Pin (PWRDN) 3.8 Positive Bus Voltage Pin (VBUS+) 4.0 Device Description 4.1 Definitions 4.2 Detailed Description 4.3 Voltage Measurement EQUATION 4-1: 4.4 Current Measurement 4.5 Selecting RSHUNT Values EQUATION 4-2: EQUATION 4-3: EQUATION 4-4: 4.6 FSR/2 Modes TABLE 4-1: FSR/2 – VBUS TABLE 4-2: FSR/2 – VSENSE 4.7 ADC Measurements, Offset and Averaging 4.8 Power and Energy EQUATION 4-5: EQUATION 4-6: EQUATION 4-7: EQUATION 4-8: 4.9 Conversion Cycles 4.10 Alert Functionality 5.0 SMBus and I2C Communications Protocols FIGURE 5-1: SMBus Timing Diagram. 5.1 Addressing and Control Bits TABLE 5-1: Address Select 5.2 SMBus Timeout 5.3 SMBus and I2C Compatibility 5.4 SMBus and I2C Standard Protocol TABLE 5-2: Protocol Packet 5.5 Auto-incrementing Pointer FIGURE 5-2: READ and WRITE Auto-incrementing Loops. 5.6 SMBus/I2C Commands TABLE 5-3: Refresh and Refresh_V Commands TABLE 5-4: General Call Response TABLE 5-5: Write Byte TABLE 5-6: Read Byte TABLE 5-7: Send Byte TABLE 5-8: Receive Byte TABLE 5-9: Block Write – I2C version TABLE 5-10: Block Read – I2C Version TABLE 5-11: Block Read – SMBus Version (Must set BYTE COUNT bit) 6.0 Register Description TABLE 6-1: PAC1711 Registers 6.1 Reading Data Bytes 6.2 Register Categories 6.3 Detailed Register Information Register 6-1: REFRESH (Address 00h) FIGURE 6-1: Host Read Period After a Refresh Command. Register 6-2: CONTROL (Address 01h) Register 6-3: ACC_COUNT (Address 02h) Register 6-4: VACC (Address 03h) Register 6-5: VBUS (Address 04h) Register 6-6: VSENSE (Address 05h) Register 6-7: VBUS_AVG (Address 06h) Register 6-8: VSENSE_AVG (Address 07h) Register 6-9: VPOWER (Address 08h) Register 6-10: VBUS_MIN (Address 09h) Register 6-11: VBUS_MAX (Address 0Ah) Register 6-12: VSENSE_MIN (Address 0Bh) Register 6-13: VSENSE_MAX (Address 0Ch) Register 6-14: VPOWER_MIN (Address 0Dh) Register 6-15: VPOWER_MAX (Address 0Eh) Register 6-16: CONTROL_LAT (Address 0Fh) Register 6-17: NEG_PWR_FSR_LAT (Address 10h) Register 6-18: ALERT_STATUS (Address 11h) Register 6-19: SMBUS_SETTINGS (Address 12h) Register 6-20: NEG_PWR_FSR (Address 13h) Register 6-21: REFRESH_G (Address 14h) Register 6-22: REFRESH_V (Address 15h) Register 6-23: SLOW (Address 16h) Register 6-24: CONTROL_ACT (Address 17h) Register 6-25: NEG_PWR_FSR_ACT (Address 18h) Register 6-26: SLOW_ALERT0 (Address 19h) Register 6-27: GPIO_ALERT1 (Address 1Ah) Register 6-28: ACC_FULL_LIMIT (Address 1BH) Register 6-29: OC_LIMIT (Address 1CH) Register 6-30: UC_LIMIT (Address 1DH) Register 6-31: OP_WARNING_LIMIT (Address 1EH) Register 6-32: OP_CRITICAL_LIMIT (Address 1FH) Register 6-33: OV_LIMIT (Address 20H) Register 6-34: UV_LIMIT (Address 21H) Register 6-35: STEP_LIMIT (Address 22H) Register 6-36: N-SAMPLES_LIMIT (Address 23h) Register 6-37: ALERT_ENABLE (Address 24h) Register 6-38: ACC_COUNT_PRESET (Address 25h) Register 6-39: VACC_PRESET (Address 26h) Register 6-40: PRODUCT_ID (Address FDh) Register 6-41: MANUFACTURER_ID (Address FEh) Register 6-42: REVISION_ID (Address FFh) 7.0 Packaging Information 7.1 Package Marking Information 7.2 Package Drawings Appendix A: Revision History Revision A (October 2025) Product Identification System Microchip Information Trademarks Legal Notice Microchip Devices Code Protection Feature