Datasheet PAC1711 (Microchip)
| 制造商 | Microchip |
| 描述 | 42V Power Monitor with I2C and Alert, 12--bit |
| 页数 / 页 | 91 / 1 — PAC1711. Single-Channel Power Monitor with Accumulator,. 42V Full Scale … |
| 文件格式/大小 | PDF / 2.0 Mb |
| 文件语言 | 英语 |
PAC1711. Single-Channel Power Monitor with Accumulator,. 42V Full Scale Range. Features. • 10-Lead VDFN Only Features:
该数据表的模型线
文件文字版本
PAC1711 Single-Channel Power Monitor with Accumulator, 42V Full Scale Range Features
• Available Packages: ◦ 3x3 mm 8-Lead VDFN with Multiple Exposed • 100 µA Active Current when Sampling at 1,024 sps Pads and Stepped Wettable Flanks • High-Side Current Monitor with a Single Channel: ◦ 3x3 mm 10-Lead VDFN ◦ 100 mV Full Scale Range (FSR) for Sense Input
• 10-Lead VDFN Only Features:
Voltage (VSENSE) with 12-bit Resolution ◦ Hardware Controlled Power-down Mode ◦ Selectable Bipolar Current Sense Capability: ◦ Low-side Power Monitor ¤ -42V to +42V Bus Voltage (VBUS) FSR ¤ -100 mV to + 100 mV FSR
Applications
(12-bit 2’s Complement Data Format) ¤ -50 mV to +50 mV Programmable FSR/2 • Low Current General Purpose Applications ◦ Very Low Input Current Simplifies Routing • Battery Powered Applications • Voltage Monitor with Wide V • Portable and Embedded Computing BUS Range: ◦ 0V to 42V FSR • Smart Home and Smart City Applications ◦ 21V Programmable FSR/2 Option • USB Type-A, Type-B and Type-C Connectivity • Real Time Auto-calibration of Offset Error for • Networking Voltage and Current; No User Adjustment • Automotive • 1% Power Measurement Accuracy over a Wide • Internet of Things (IoT) Dynamic Range • On-chip Accumulation of 24-bit Results for Power
Description
Measurement: PAC1711 is a single-channel power monitor with a bus ◦ 56-bit Power Accumulator Register for Recording voltage monitor and current sense amplifier that feed Accumulated Power Data into a 12-bit resolution Analog-to-Digital Converter ◦ 32-bit Accumulator Count Register (ADC). Designed for high side current sensing, its • User Programmable Sample Rates (ƒ digital circuitry performs power calculations and energy S) of 8, 64, 256, 1024, 4096 and 8192 sps accumulation. This enables the device to monitor ◦ User Programmable ƒ power with integration periods up to one year or longer. S = 16,384 sps for VBUS or VSENSE (only one option at a time) The device stores bus voltage (VBUS), shunt resistor ◦ Single-shot Modes using Refresh Commands or voltage (VSENSE) and accumulated proportional power General Purpose Input/Output (GPIO) (VPOWER) data. The embedded controller or system • SLOW Pin for Improved Low Power Mode host can read the PAC1711 registers and retrieve the stored data. • 2.7V to 5.5V Supply Operation: ◦ 1.62V to 5.5V Capable I2C/SMBus and Digital I/O PAC1711 includes a configurable alert system that can trigger alerts when the device detects voltage, current ◦ SMBus 3.1 and I2C Fast-mode Plus (1 MHz) or power excursions. ◦ I2C High-speed Mode (3.4 MHz) Configure the sample rate, power integration period, • SMBus Address – 16 Options one-shot measurement settings and other controls • A0/A1 Pins can Function as ALERT Pins for using SMBus or I2C communication. Specific Addresses PAC1711 uses real-time calibration to minimize offset • No Input Filters Required error. No input filters are required for this device. The • Step Limit for Average Variation Detection built-in adjustable averaging function produces very • Patent Pending Addressing Alert Scheme low noise, high resolution measurement results. • Alerts Can Be Enabled for Accumulator Overflow, The 10-Lead VDFN PAC1711 package has a VBUS+ Conversion Cycle Complete and Limit Excursions pin that enables low-side power monitoring. This allows additional power savings using a Power-down feature not available for the 8-Lead VDFN package. 2025 Microchip Technology Inc. and its subsidiaries DS20007058A-page 1 Document Outline Single-Channel Power Monitor with Accumulator, 42V Full Scale Range Features Applications Description Package Types Functional Block Diagram 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings (†) FIGURE 1-1: PAC1711 ESD Protection Circuitry. 1.2 DC Electrical Specifications 1.3 AC Electrical Specifications 1.4 Temperature Specifications 2.0 Typical Performance Curves FIGURE 2-1: VSENSE Error vs. VSENSE, TA = 25°C, Multiple VDD, Unipolar Mode. FIGURE 2-2: VSENSE Error vs. VSENSE, TA = 25°C, Multiple VDD, Bipolar FSR Mode. FIGURE 2-3: VSENSE Error vs. VSENSE, VDD = 5.5V, Multiple TA, Bipolar FSR Mode. FIGURE 2-4: VSENSE Error vs. VSENSE, VDD = 2.7V, Multiple TA, Bipolar FSR Mode. FIGURE 2-5: VSENSE Error vs. VSENSE, VDD = 5.5V, Multiple TA, Unipolar Mode. FIGURE 2-6: VSENSE Error vs. VSENSE, VDD = 2.7V, Multiple TA, Unipolar Mode. FIGURE 2-7: VSENSE Error vs. VSENSE, VDD = 5.5V, Multiple TA, Unipolar Mode, Logarithmic Scale. FIGURE 2-8: VSENSE Error vs. VSENSE, VDD = 2.7V, Multiple TA, Unipolar Mode, Logarithmic Scale. FIGURE 2-9: VSENSE Error vs. VSENSE, VDD = 5.5V, Multiple TA, Bipolar FSR Mode, Zoom View. FIGURE 2-10: VSENSE Error vs. VSENSE, VDD = 2.7V, Multiple TA, Bipolar FSR Mode, Zoom View. FIGURE 2-11: VBUS Error vs. VBUS, TA = 25°C, Multiple VDD, Unipolar Mode, Logarithmic Scale. FIGURE 2-12: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Unipolar Mode, Logarithmic Scale. FIGURE 2-13: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Unipolar Mode, Logarithmic Scale, Zoom View. FIGURE 2-14: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Bipolar FSR Mode. FIGURE 2-15: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Bipolar FSR Mode, Zoom View. FIGURE 2-16: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Bipolar FSR Mode. FIGURE 2-17: VSENSE Zero Input Histogram, Bipolar FSR/2 Mode (n = 10,000 total samples, 8x average). FIGURE 2-18: VBUS Zero Input Histogram, Bipolar FSR/2 Mode (n = 28,000 total samples, 8x average). FIGURE 2-19: VBUS Offset vs. TA, VDD = 3.3V, Bipolar FSR Mode. FIGURE 2-20: VSENSE DC Offset vs. TA, VBUS = 10.5V, Bipolar FSR Mode. FIGURE 2-21: IDD at 1,024 sps vs. TA, Multiple VDD. FIGURE 2-22: IDD in Slow Mode vs. TA, Multiple VDD. FIGURE 2-23: IDD at 8,192 sps vs. TA, Multiple VDD. FIGURE 2-24: IDD vs. TA, Multiple VDD, Multiple Sample Rates. FIGURE 2-25: IDD in Sleep Mode vs. TA, Multiple VDD. FIGURE 2-26: IDD in Power-down Mode vs. TA, Multiple VDD. FIGURE 2-27: ISENSE- vs. TA, Common Mode, Multiple VBUS. FIGURE 2-28: ISENSE+ vs. TA, Common Mode, Multiple VBUS. FIGURE 2-29: VSENSE- Leakage vs. TA, Common Mode, Multiple VBUS. FIGURE 2-30: VSENSE+ Leakage vs. TA, Common Mode, Multiple VBUS. FIGURE 2-31: IOL vs. VOL, TA = 25°C, VDD = 5.5V. FIGURE 2-32: Sample Rate (ƒS) Error across TA = -40°C to +125°C, n = 30,852 Total Samples. FIGURE 2-33: Sample Rate (ƒS) Error across TA = 30°C, n = 10,308 Total Samples. FIGURE 2-34: POR Threshold vs. TA. 3.0 Pin Descriptions TABLE 3-1: PAC1711 Pin Descriptions 3.1 Sense Voltage Pins (VSENSE+ and VSENSE–) 3.2 Ground Pin (GND) 3.3 Positive Power Supply Voltage Pin (VDD) 3.4 SMBus Data (SMBDAT) Pin (SDA) 3.5 SMBus Clock (SMBCLK) Pin (SCL) 3.6 A0 and A1 Multi-functional Pins 3.7 Power-down Pin (PWRDN) 3.8 Positive Bus Voltage Pin (VBUS+) 4.0 Device Description 4.1 Definitions 4.2 Detailed Description 4.3 Voltage Measurement EQUATION 4-1: 4.4 Current Measurement 4.5 Selecting RSHUNT Values EQUATION 4-2: EQUATION 4-3: EQUATION 4-4: 4.6 FSR/2 Modes TABLE 4-1: FSR/2 – VBUS TABLE 4-2: FSR/2 – VSENSE 4.7 ADC Measurements, Offset and Averaging 4.8 Power and Energy EQUATION 4-5: EQUATION 4-6: EQUATION 4-7: EQUATION 4-8: 4.9 Conversion Cycles 4.10 Alert Functionality 5.0 SMBus and I2C Communications Protocols FIGURE 5-1: SMBus Timing Diagram. 5.1 Addressing and Control Bits TABLE 5-1: Address Select 5.2 SMBus Timeout 5.3 SMBus and I2C Compatibility 5.4 SMBus and I2C Standard Protocol TABLE 5-2: Protocol Packet 5.5 Auto-incrementing Pointer FIGURE 5-2: READ and WRITE Auto-incrementing Loops. 5.6 SMBus/I2C Commands TABLE 5-3: Refresh and Refresh_V Commands TABLE 5-4: General Call Response TABLE 5-5: Write Byte TABLE 5-6: Read Byte TABLE 5-7: Send Byte TABLE 5-8: Receive Byte TABLE 5-9: Block Write – I2C version TABLE 5-10: Block Read – I2C Version TABLE 5-11: Block Read – SMBus Version (Must set BYTE COUNT bit) 6.0 Register Description TABLE 6-1: PAC1711 Registers 6.1 Reading Data Bytes 6.2 Register Categories 6.3 Detailed Register Information Register 6-1: REFRESH (Address 00h) FIGURE 6-1: Host Read Period After a Refresh Command. Register 6-2: CONTROL (Address 01h) Register 6-3: ACC_COUNT (Address 02h) Register 6-4: VACC (Address 03h) Register 6-5: VBUS (Address 04h) Register 6-6: VSENSE (Address 05h) Register 6-7: VBUS_AVG (Address 06h) Register 6-8: VSENSE_AVG (Address 07h) Register 6-9: VPOWER (Address 08h) Register 6-10: VBUS_MIN (Address 09h) Register 6-11: VBUS_MAX (Address 0Ah) Register 6-12: VSENSE_MIN (Address 0Bh) Register 6-13: VSENSE_MAX (Address 0Ch) Register 6-14: VPOWER_MIN (Address 0Dh) Register 6-15: VPOWER_MAX (Address 0Eh) Register 6-16: CONTROL_LAT (Address 0Fh) Register 6-17: NEG_PWR_FSR_LAT (Address 10h) Register 6-18: ALERT_STATUS (Address 11h) Register 6-19: SMBUS_SETTINGS (Address 12h) Register 6-20: NEG_PWR_FSR (Address 13h) Register 6-21: REFRESH_G (Address 14h) Register 6-22: REFRESH_V (Address 15h) Register 6-23: SLOW (Address 16h) Register 6-24: CONTROL_ACT (Address 17h) Register 6-25: NEG_PWR_FSR_ACT (Address 18h) Register 6-26: SLOW_ALERT0 (Address 19h) Register 6-27: GPIO_ALERT1 (Address 1Ah) Register 6-28: ACC_FULL_LIMIT (Address 1BH) Register 6-29: OC_LIMIT (Address 1CH) Register 6-30: UC_LIMIT (Address 1DH) Register 6-31: OP_WARNING_LIMIT (Address 1EH) Register 6-32: OP_CRITICAL_LIMIT (Address 1FH) Register 6-33: OV_LIMIT (Address 20H) Register 6-34: UV_LIMIT (Address 21H) Register 6-35: STEP_LIMIT (Address 22H) Register 6-36: N-SAMPLES_LIMIT (Address 23h) Register 6-37: ALERT_ENABLE (Address 24h) Register 6-38: ACC_COUNT_PRESET (Address 25h) Register 6-39: VACC_PRESET (Address 26h) Register 6-40: PRODUCT_ID (Address FDh) Register 6-41: MANUFACTURER_ID (Address FEh) Register 6-42: REVISION_ID (Address FFh) 7.0 Packaging Information 7.1 Package Marking Information 7.2 Package Drawings Appendix A: Revision History Revision A (October 2025) Product Identification System Microchip Information Trademarks Legal Notice Microchip Devices Code Protection Feature
• Available Packages: ◦ 3x3 mm 8-Lead VDFN with Multiple Exposed • 100 µA Active Current when Sampling at 1,024 sps Pads and Stepped Wettable Flanks • High-Side Current Monitor with a Single Channel: ◦ 3x3 mm 10-Lead VDFN ◦ 100 mV Full Scale Range (FSR) for Sense Input
• 10-Lead VDFN Only Features:
Voltage (VSENSE) with 12-bit Resolution ◦ Hardware Controlled Power-down Mode ◦ Selectable Bipolar Current Sense Capability: ◦ Low-side Power Monitor ¤ -42V to +42V Bus Voltage (VBUS) FSR ¤ -100 mV to + 100 mV FSR
Applications
(12-bit 2’s Complement Data Format) ¤ -50 mV to +50 mV Programmable FSR/2 • Low Current General Purpose Applications ◦ Very Low Input Current Simplifies Routing • Battery Powered Applications • Voltage Monitor with Wide V • Portable and Embedded Computing BUS Range: ◦ 0V to 42V FSR • Smart Home and Smart City Applications ◦ 21V Programmable FSR/2 Option • USB Type-A, Type-B and Type-C Connectivity • Real Time Auto-calibration of Offset Error for • Networking Voltage and Current; No User Adjustment • Automotive • 1% Power Measurement Accuracy over a Wide • Internet of Things (IoT) Dynamic Range • On-chip Accumulation of 24-bit Results for Power
Description
Measurement: PAC1711 is a single-channel power monitor with a bus ◦ 56-bit Power Accumulator Register for Recording voltage monitor and current sense amplifier that feed Accumulated Power Data into a 12-bit resolution Analog-to-Digital Converter ◦ 32-bit Accumulator Count Register (ADC). Designed for high side current sensing, its • User Programmable Sample Rates (ƒ digital circuitry performs power calculations and energy S) of 8, 64, 256, 1024, 4096 and 8192 sps accumulation. This enables the device to monitor ◦ User Programmable ƒ power with integration periods up to one year or longer. S = 16,384 sps for VBUS or VSENSE (only one option at a time) The device stores bus voltage (VBUS), shunt resistor ◦ Single-shot Modes using Refresh Commands or voltage (VSENSE) and accumulated proportional power General Purpose Input/Output (GPIO) (VPOWER) data. The embedded controller or system • SLOW Pin for Improved Low Power Mode host can read the PAC1711 registers and retrieve the stored data. • 2.7V to 5.5V Supply Operation: ◦ 1.62V to 5.5V Capable I2C/SMBus and Digital I/O PAC1711 includes a configurable alert system that can trigger alerts when the device detects voltage, current ◦ SMBus 3.1 and I2C Fast-mode Plus (1 MHz) or power excursions. ◦ I2C High-speed Mode (3.4 MHz) Configure the sample rate, power integration period, • SMBus Address – 16 Options one-shot measurement settings and other controls • A0/A1 Pins can Function as ALERT Pins for using SMBus or I2C communication. Specific Addresses PAC1711 uses real-time calibration to minimize offset • No Input Filters Required error. No input filters are required for this device. The • Step Limit for Average Variation Detection built-in adjustable averaging function produces very • Patent Pending Addressing Alert Scheme low noise, high resolution measurement results. • Alerts Can Be Enabled for Accumulator Overflow, The 10-Lead VDFN PAC1711 package has a VBUS+ Conversion Cycle Complete and Limit Excursions pin that enables low-side power monitoring. This allows additional power savings using a Power-down feature not available for the 8-Lead VDFN package. 2025 Microchip Technology Inc. and its subsidiaries DS20007058A-page 1 Document Outline Single-Channel Power Monitor with Accumulator, 42V Full Scale Range Features Applications Description Package Types Functional Block Diagram 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings (†) FIGURE 1-1: PAC1711 ESD Protection Circuitry. 1.2 DC Electrical Specifications 1.3 AC Electrical Specifications 1.4 Temperature Specifications 2.0 Typical Performance Curves FIGURE 2-1: VSENSE Error vs. VSENSE, TA = 25°C, Multiple VDD, Unipolar Mode. FIGURE 2-2: VSENSE Error vs. VSENSE, TA = 25°C, Multiple VDD, Bipolar FSR Mode. FIGURE 2-3: VSENSE Error vs. VSENSE, VDD = 5.5V, Multiple TA, Bipolar FSR Mode. FIGURE 2-4: VSENSE Error vs. VSENSE, VDD = 2.7V, Multiple TA, Bipolar FSR Mode. FIGURE 2-5: VSENSE Error vs. VSENSE, VDD = 5.5V, Multiple TA, Unipolar Mode. FIGURE 2-6: VSENSE Error vs. VSENSE, VDD = 2.7V, Multiple TA, Unipolar Mode. FIGURE 2-7: VSENSE Error vs. VSENSE, VDD = 5.5V, Multiple TA, Unipolar Mode, Logarithmic Scale. FIGURE 2-8: VSENSE Error vs. VSENSE, VDD = 2.7V, Multiple TA, Unipolar Mode, Logarithmic Scale. FIGURE 2-9: VSENSE Error vs. VSENSE, VDD = 5.5V, Multiple TA, Bipolar FSR Mode, Zoom View. FIGURE 2-10: VSENSE Error vs. VSENSE, VDD = 2.7V, Multiple TA, Bipolar FSR Mode, Zoom View. FIGURE 2-11: VBUS Error vs. VBUS, TA = 25°C, Multiple VDD, Unipolar Mode, Logarithmic Scale. FIGURE 2-12: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Unipolar Mode, Logarithmic Scale. FIGURE 2-13: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Unipolar Mode, Logarithmic Scale, Zoom View. FIGURE 2-14: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Bipolar FSR Mode. FIGURE 2-15: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Bipolar FSR Mode, Zoom View. FIGURE 2-16: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Bipolar FSR Mode. FIGURE 2-17: VSENSE Zero Input Histogram, Bipolar FSR/2 Mode (n = 10,000 total samples, 8x average). FIGURE 2-18: VBUS Zero Input Histogram, Bipolar FSR/2 Mode (n = 28,000 total samples, 8x average). FIGURE 2-19: VBUS Offset vs. TA, VDD = 3.3V, Bipolar FSR Mode. FIGURE 2-20: VSENSE DC Offset vs. TA, VBUS = 10.5V, Bipolar FSR Mode. FIGURE 2-21: IDD at 1,024 sps vs. TA, Multiple VDD. FIGURE 2-22: IDD in Slow Mode vs. TA, Multiple VDD. FIGURE 2-23: IDD at 8,192 sps vs. TA, Multiple VDD. FIGURE 2-24: IDD vs. TA, Multiple VDD, Multiple Sample Rates. FIGURE 2-25: IDD in Sleep Mode vs. TA, Multiple VDD. FIGURE 2-26: IDD in Power-down Mode vs. TA, Multiple VDD. FIGURE 2-27: ISENSE- vs. TA, Common Mode, Multiple VBUS. FIGURE 2-28: ISENSE+ vs. TA, Common Mode, Multiple VBUS. FIGURE 2-29: VSENSE- Leakage vs. TA, Common Mode, Multiple VBUS. FIGURE 2-30: VSENSE+ Leakage vs. TA, Common Mode, Multiple VBUS. FIGURE 2-31: IOL vs. VOL, TA = 25°C, VDD = 5.5V. FIGURE 2-32: Sample Rate (ƒS) Error across TA = -40°C to +125°C, n = 30,852 Total Samples. FIGURE 2-33: Sample Rate (ƒS) Error across TA = 30°C, n = 10,308 Total Samples. FIGURE 2-34: POR Threshold vs. TA. 3.0 Pin Descriptions TABLE 3-1: PAC1711 Pin Descriptions 3.1 Sense Voltage Pins (VSENSE+ and VSENSE–) 3.2 Ground Pin (GND) 3.3 Positive Power Supply Voltage Pin (VDD) 3.4 SMBus Data (SMBDAT) Pin (SDA) 3.5 SMBus Clock (SMBCLK) Pin (SCL) 3.6 A0 and A1 Multi-functional Pins 3.7 Power-down Pin (PWRDN) 3.8 Positive Bus Voltage Pin (VBUS+) 4.0 Device Description 4.1 Definitions 4.2 Detailed Description 4.3 Voltage Measurement EQUATION 4-1: 4.4 Current Measurement 4.5 Selecting RSHUNT Values EQUATION 4-2: EQUATION 4-3: EQUATION 4-4: 4.6 FSR/2 Modes TABLE 4-1: FSR/2 – VBUS TABLE 4-2: FSR/2 – VSENSE 4.7 ADC Measurements, Offset and Averaging 4.8 Power and Energy EQUATION 4-5: EQUATION 4-6: EQUATION 4-7: EQUATION 4-8: 4.9 Conversion Cycles 4.10 Alert Functionality 5.0 SMBus and I2C Communications Protocols FIGURE 5-1: SMBus Timing Diagram. 5.1 Addressing and Control Bits TABLE 5-1: Address Select 5.2 SMBus Timeout 5.3 SMBus and I2C Compatibility 5.4 SMBus and I2C Standard Protocol TABLE 5-2: Protocol Packet 5.5 Auto-incrementing Pointer FIGURE 5-2: READ and WRITE Auto-incrementing Loops. 5.6 SMBus/I2C Commands TABLE 5-3: Refresh and Refresh_V Commands TABLE 5-4: General Call Response TABLE 5-5: Write Byte TABLE 5-6: Read Byte TABLE 5-7: Send Byte TABLE 5-8: Receive Byte TABLE 5-9: Block Write – I2C version TABLE 5-10: Block Read – I2C Version TABLE 5-11: Block Read – SMBus Version (Must set BYTE COUNT bit) 6.0 Register Description TABLE 6-1: PAC1711 Registers 6.1 Reading Data Bytes 6.2 Register Categories 6.3 Detailed Register Information Register 6-1: REFRESH (Address 00h) FIGURE 6-1: Host Read Period After a Refresh Command. Register 6-2: CONTROL (Address 01h) Register 6-3: ACC_COUNT (Address 02h) Register 6-4: VACC (Address 03h) Register 6-5: VBUS (Address 04h) Register 6-6: VSENSE (Address 05h) Register 6-7: VBUS_AVG (Address 06h) Register 6-8: VSENSE_AVG (Address 07h) Register 6-9: VPOWER (Address 08h) Register 6-10: VBUS_MIN (Address 09h) Register 6-11: VBUS_MAX (Address 0Ah) Register 6-12: VSENSE_MIN (Address 0Bh) Register 6-13: VSENSE_MAX (Address 0Ch) Register 6-14: VPOWER_MIN (Address 0Dh) Register 6-15: VPOWER_MAX (Address 0Eh) Register 6-16: CONTROL_LAT (Address 0Fh) Register 6-17: NEG_PWR_FSR_LAT (Address 10h) Register 6-18: ALERT_STATUS (Address 11h) Register 6-19: SMBUS_SETTINGS (Address 12h) Register 6-20: NEG_PWR_FSR (Address 13h) Register 6-21: REFRESH_G (Address 14h) Register 6-22: REFRESH_V (Address 15h) Register 6-23: SLOW (Address 16h) Register 6-24: CONTROL_ACT (Address 17h) Register 6-25: NEG_PWR_FSR_ACT (Address 18h) Register 6-26: SLOW_ALERT0 (Address 19h) Register 6-27: GPIO_ALERT1 (Address 1Ah) Register 6-28: ACC_FULL_LIMIT (Address 1BH) Register 6-29: OC_LIMIT (Address 1CH) Register 6-30: UC_LIMIT (Address 1DH) Register 6-31: OP_WARNING_LIMIT (Address 1EH) Register 6-32: OP_CRITICAL_LIMIT (Address 1FH) Register 6-33: OV_LIMIT (Address 20H) Register 6-34: UV_LIMIT (Address 21H) Register 6-35: STEP_LIMIT (Address 22H) Register 6-36: N-SAMPLES_LIMIT (Address 23h) Register 6-37: ALERT_ENABLE (Address 24h) Register 6-38: ACC_COUNT_PRESET (Address 25h) Register 6-39: VACC_PRESET (Address 26h) Register 6-40: PRODUCT_ID (Address FDh) Register 6-41: MANUFACTURER_ID (Address FEh) Register 6-42: REVISION_ID (Address FFh) 7.0 Packaging Information 7.1 Package Marking Information 7.2 Package Drawings Appendix A: Revision History Revision A (October 2025) Product Identification System Microchip Information Trademarks Legal Notice Microchip Devices Code Protection Feature