Datasheet TB9084FTG (Toshiba) - 7
| 制造商 | Toshiba |
| 描述 | Pre-driver for automobile |
| 页数 / 页 | 78 / 7 — 7.2. Gate Driver Circuits. 7.2.1. Gate Drivers for Driving 3-Phase FETs |
| 修订版 | 3.0 |
| 文件格式/大小 | PDF / 3.7 Mb |
| 文件语言 | 英语 |
7.2. Gate Driver Circuits. 7.2.1. Gate Drivers for Driving 3-Phase FETs
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TB9084FTG
7.2. Gate Driver Circuits
As a gate driver to drive external FETs (7 units), this product is equipped with gate drivers (6 units) for 3- phase FETs and a gate driver (1 unit) for a FET for reverse polality protection.
7.2.1. Gate Drivers for Driving 3-Phase FETs
The gate driver circuits for 3-phase FETs are for high-side drive and low-side drive for motor drive. Each of the gate driver circuits for high-side drive and low-side drive has an input terminal. This input terminal turns off the gate driver when an open fault happens. The gate driver circuit has 6 output terminals to drive a 3-phase FET. The output stage configuration is of a switch type, and an external series resistor is recommended depending on the operation speed needed for the 3-phase FET. For a gate driver that drives a high-side FET, when VB voltage is high enough, voltage clamped at H*S reference +10V is output. When VB voltage is low, charge pump voltage with GND reference is output via an internal switch so that enough voltage is applied to the FET gate, and the output voltage is 20V or lower not exceeding the Vgs withstand voltage of the FET. On the other hand, since a gate driver that drives a low-side FET is given Vcp power supply voltage enough to drive in the Vb operating voltage range, voltage clamped at LS reference +11V is always output. These outputs have electric current capability suitable for controlling FET gate that drives motors for applications shown in Chapter 2, and the propagation delay time from the input terminal to the output terminal and the relative deference time for on/off time and off/on time of high side and low side respectively on each phase are optimized. In addition, it has a pull-down resistor to stably turn the FET on and off while the motor’s phase input is in Hi-Z state. Note that when a 3-phase FET is turned off, the effect of the electric current from H*S terminal of this product on the motor operation is negligible. H*S terminal and LS terminal are robust enough against noise exceeding VB and noise below GND. © 2 025 7 2025-07-31 Toshiba Electronic Devices & Storage Corporation Rev. 3.0 Document Outline 1. Description 2. Applications 3. Features 4. Block Diagram 5. Pin Assignments Top view 6. Pin Description 7. Functional Description 7.1. Charge Pump Circuit 7.2. Gate Driver Circuits 7.2.1. Gate Drivers for Driving 3-Phase FETs 7.2.2. Gate Driver for FET for Reverse Polarity Protection 7.3. Current Sensing Circuit 7.3.1. Configuration 7.3.2. Offset Calibration 7.4. Oscillation Circuit 7.5. Abnormality Flag Output Function 7.5.1. NDIAG Terminal Output 7.5.2. Status Registers in SPI communication 7.6. Abnormality Detection Circuits 7.6.1. VCC Under Voltage Detection Function 7.6.2. VB Under Voltage Detection Function 7.6.3. RPPO Under Voltage Detection Function 7.6.4. VCC Over Voltage Detection Function 7.6.5. VCP Over Voltage Detection Function 7.6.6. Over temperature Detection Function 7.6.7. VDS Detection Function for 3-Phase FETs 7.6.8. Abnormality Detection for CP1SW and CP2SW Terminals 7.7. Alarm Input Circuit 7.8. SPI Communication Circuit 7.8.1. SPI Communication Operation 7.8.2. Error Judgment 7.8.3. Register Map 7.8.3.1. CONFIG1 Write Address=2h / Read Address=3h 7.8.3.2. CONFIG2 Write Address=4h / Read Address=5h 7.8.3.3. CONFIG3 Write Address=6h / Read Address=7h 7.8.3.4. CONFIG4 (Write Address=8h / Read Address=9h 7.8.3.5. CONFIG5 Write Address=Ah / Read Address=Bh 7.8.3.6. STAT1 / Read Address=Dh 7.8.3.7. STAT2 / Read Address=Fh 7.8.3.8. STAT1_CLR Write Address=10h 7.8.3.9. STAT2_CLR Write Address=12h 7.8.3.10. NOP Write Address=Fh / Read Address=Fh 8. Absolute Maximum Ratings (Ta = 25 C) 9. Electrical Characteristics 9.1. Operating Voltage Ranges 9.2. Consumption Current 9.3. Charge Pump Circuit 9.4. Gate Driver Circuits 9.5. Current Sense Amplifier Circuit 9.6. Oscillation Circuit 9.7. Abnormality Detection Circuits 9.8. Alarm Input Circuit 9.9. SPI Communication Circuit 10. Application Circuit Example 11. Package Outlines 12. Revision History 13. Abbreviation Collection RESTRICTIONS ON PRODUCT USE
7.2. Gate Driver Circuits
As a gate driver to drive external FETs (7 units), this product is equipped with gate drivers (6 units) for 3- phase FETs and a gate driver (1 unit) for a FET for reverse polality protection.
7.2.1. Gate Drivers for Driving 3-Phase FETs
The gate driver circuits for 3-phase FETs are for high-side drive and low-side drive for motor drive. Each of the gate driver circuits for high-side drive and low-side drive has an input terminal. This input terminal turns off the gate driver when an open fault happens. The gate driver circuit has 6 output terminals to drive a 3-phase FET. The output stage configuration is of a switch type, and an external series resistor is recommended depending on the operation speed needed for the 3-phase FET. For a gate driver that drives a high-side FET, when VB voltage is high enough, voltage clamped at H*S reference +10V is output. When VB voltage is low, charge pump voltage with GND reference is output via an internal switch so that enough voltage is applied to the FET gate, and the output voltage is 20V or lower not exceeding the Vgs withstand voltage of the FET. On the other hand, since a gate driver that drives a low-side FET is given Vcp power supply voltage enough to drive in the Vb operating voltage range, voltage clamped at LS reference +11V is always output. These outputs have electric current capability suitable for controlling FET gate that drives motors for applications shown in Chapter 2, and the propagation delay time from the input terminal to the output terminal and the relative deference time for on/off time and off/on time of high side and low side respectively on each phase are optimized. In addition, it has a pull-down resistor to stably turn the FET on and off while the motor’s phase input is in Hi-Z state. Note that when a 3-phase FET is turned off, the effect of the electric current from H*S terminal of this product on the motor operation is negligible. H*S terminal and LS terminal are robust enough against noise exceeding VB and noise below GND. © 2 025 7 2025-07-31 Toshiba Electronic Devices & Storage Corporation Rev. 3.0 Document Outline 1. Description 2. Applications 3. Features 4. Block Diagram 5. Pin Assignments Top view 6. Pin Description 7. Functional Description 7.1. Charge Pump Circuit 7.2. Gate Driver Circuits 7.2.1. Gate Drivers for Driving 3-Phase FETs 7.2.2. Gate Driver for FET for Reverse Polarity Protection 7.3. Current Sensing Circuit 7.3.1. Configuration 7.3.2. Offset Calibration 7.4. Oscillation Circuit 7.5. Abnormality Flag Output Function 7.5.1. NDIAG Terminal Output 7.5.2. Status Registers in SPI communication 7.6. Abnormality Detection Circuits 7.6.1. VCC Under Voltage Detection Function 7.6.2. VB Under Voltage Detection Function 7.6.3. RPPO Under Voltage Detection Function 7.6.4. VCC Over Voltage Detection Function 7.6.5. VCP Over Voltage Detection Function 7.6.6. Over temperature Detection Function 7.6.7. VDS Detection Function for 3-Phase FETs 7.6.8. Abnormality Detection for CP1SW and CP2SW Terminals 7.7. Alarm Input Circuit 7.8. SPI Communication Circuit 7.8.1. SPI Communication Operation 7.8.2. Error Judgment 7.8.3. Register Map 7.8.3.1. CONFIG1 Write Address=2h / Read Address=3h 7.8.3.2. CONFIG2 Write Address=4h / Read Address=5h 7.8.3.3. CONFIG3 Write Address=6h / Read Address=7h 7.8.3.4. CONFIG4 (Write Address=8h / Read Address=9h 7.8.3.5. CONFIG5 Write Address=Ah / Read Address=Bh 7.8.3.6. STAT1 / Read Address=Dh 7.8.3.7. STAT2 / Read Address=Fh 7.8.3.8. STAT1_CLR Write Address=10h 7.8.3.9. STAT2_CLR Write Address=12h 7.8.3.10. NOP Write Address=Fh / Read Address=Fh 8. Absolute Maximum Ratings (Ta = 25 C) 9. Electrical Characteristics 9.1. Operating Voltage Ranges 9.2. Consumption Current 9.3. Charge Pump Circuit 9.4. Gate Driver Circuits 9.5. Current Sense Amplifier Circuit 9.6. Oscillation Circuit 9.7. Abnormality Detection Circuits 9.8. Alarm Input Circuit 9.9. SPI Communication Circuit 10. Application Circuit Example 11. Package Outlines 12. Revision History 13. Abbreviation Collection RESTRICTIONS ON PRODUCT USE