Datasheet TB9084FTG (Toshiba) - 6
| 制造商 | Toshiba |
| 描述 | Pre-driver for automobile |
| 页数 / 页 | 78 / 6 — 7. Functional Description. 7.1. Charge Pump Circuit. Fig. 7.1 Charge Pump … |
| 修订版 | 3.0 |
| 文件格式/大小 | PDF / 3.7 Mb |
| 文件语言 | 英语 |
7. Functional Description. 7.1. Charge Pump Circuit. Fig. 7.1 Charge Pump Circuit Block Diagram
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7. Functional Description 7.1. Charge Pump Circuit
This product has a built-in charge pump circuit for the gate drivers to drive 3-phase FETs. The drive frequency is 250kHz (Typ.) as long as the switching operation is not stopped. With this drive frequency, the VB voltage is pumped up. The charge pump circuit requires two external ceramic capacitors. The pumping up operation in the the circuit stops under the conditions below. When Vcp > Vb+12V (Typ.) so that Vcp is not above the Vgs rating (±20V) of the 3-phase FET, its switching operation is stopped by the control of the internal circuit, and when Vcp≤Vb+12V (Typ.), its operation is resumed. When Vb voltage is low and Vcp is lower than Vb+12V (Typ.), Vcp outputs characteristics depending on the charge pump circuit configuration and its capability. In addition, when Vcp > 56V (Typ.) so that Vcp withstand voltage is not exceeded, detection operation is conducted depending on the register setting by SPI communication. And when Vcp≤56V (Typ.), detection release operation is conducted depending on the register setting by SPI communication as wel . For details, see Chapter 7.6.5. When the charge pump circuit is turned off after an abnormality detection, VCP voltage transitions to VB voltage. Note: When a fault is detected and the charge pump circuit is turned off and a certain period has passed after the fault release, the motor operation is enabled. Details are shown in Chapter 7.6. When the reset of this product is released, charge pump operation is started, and after the voltage has become sufficient, the gate driver operation is allowed. This sequence is to prevent the gate driver from malfunctioning. For details, see Fig. 7.6.1.2. When an adjacent short circuit or a short to VB or ground of CP1SW terminal and CP2SW happen, the internal elements are protected with the abnormality detection circuits. The details are shown in chapter 7.6.8.
Fig. 7.1 Charge Pump Circuit Block Diagram
© 2 025 6 2025-07-31 Toshiba Electronic Devices & Storage Corporation Rev. 3.0 Document Outline 1. Description 2. Applications 3. Features 4. Block Diagram 5. Pin Assignments Top view 6. Pin Description 7. Functional Description 7.1. Charge Pump Circuit 7.2. Gate Driver Circuits 7.2.1. Gate Drivers for Driving 3-Phase FETs 7.2.2. Gate Driver for FET for Reverse Polarity Protection 7.3. Current Sensing Circuit 7.3.1. Configuration 7.3.2. Offset Calibration 7.4. Oscillation Circuit 7.5. Abnormality Flag Output Function 7.5.1. NDIAG Terminal Output 7.5.2. Status Registers in SPI communication 7.6. Abnormality Detection Circuits 7.6.1. VCC Under Voltage Detection Function 7.6.2. VB Under Voltage Detection Function 7.6.3. RPPO Under Voltage Detection Function 7.6.4. VCC Over Voltage Detection Function 7.6.5. VCP Over Voltage Detection Function 7.6.6. Over temperature Detection Function 7.6.7. VDS Detection Function for 3-Phase FETs 7.6.8. Abnormality Detection for CP1SW and CP2SW Terminals 7.7. Alarm Input Circuit 7.8. SPI Communication Circuit 7.8.1. SPI Communication Operation 7.8.2. Error Judgment 7.8.3. Register Map 7.8.3.1. CONFIG1 Write Address=2h / Read Address=3h 7.8.3.2. CONFIG2 Write Address=4h / Read Address=5h 7.8.3.3. CONFIG3 Write Address=6h / Read Address=7h 7.8.3.4. CONFIG4 (Write Address=8h / Read Address=9h 7.8.3.5. CONFIG5 Write Address=Ah / Read Address=Bh 7.8.3.6. STAT1 / Read Address=Dh 7.8.3.7. STAT2 / Read Address=Fh 7.8.3.8. STAT1_CLR Write Address=10h 7.8.3.9. STAT2_CLR Write Address=12h 7.8.3.10. NOP Write Address=Fh / Read Address=Fh 8. Absolute Maximum Ratings (Ta = 25 C) 9. Electrical Characteristics 9.1. Operating Voltage Ranges 9.2. Consumption Current 9.3. Charge Pump Circuit 9.4. Gate Driver Circuits 9.5. Current Sense Amplifier Circuit 9.6. Oscillation Circuit 9.7. Abnormality Detection Circuits 9.8. Alarm Input Circuit 9.9. SPI Communication Circuit 10. Application Circuit Example 11. Package Outlines 12. Revision History 13. Abbreviation Collection RESTRICTIONS ON PRODUCT USE
7. Functional Description 7.1. Charge Pump Circuit
This product has a built-in charge pump circuit for the gate drivers to drive 3-phase FETs. The drive frequency is 250kHz (Typ.) as long as the switching operation is not stopped. With this drive frequency, the VB voltage is pumped up. The charge pump circuit requires two external ceramic capacitors. The pumping up operation in the the circuit stops under the conditions below. When Vcp > Vb+12V (Typ.) so that Vcp is not above the Vgs rating (±20V) of the 3-phase FET, its switching operation is stopped by the control of the internal circuit, and when Vcp≤Vb+12V (Typ.), its operation is resumed. When Vb voltage is low and Vcp is lower than Vb+12V (Typ.), Vcp outputs characteristics depending on the charge pump circuit configuration and its capability. In addition, when Vcp > 56V (Typ.) so that Vcp withstand voltage is not exceeded, detection operation is conducted depending on the register setting by SPI communication. And when Vcp≤56V (Typ.), detection release operation is conducted depending on the register setting by SPI communication as wel . For details, see Chapter 7.6.5. When the charge pump circuit is turned off after an abnormality detection, VCP voltage transitions to VB voltage. Note: When a fault is detected and the charge pump circuit is turned off and a certain period has passed after the fault release, the motor operation is enabled. Details are shown in Chapter 7.6. When the reset of this product is released, charge pump operation is started, and after the voltage has become sufficient, the gate driver operation is allowed. This sequence is to prevent the gate driver from malfunctioning. For details, see Fig. 7.6.1.2. When an adjacent short circuit or a short to VB or ground of CP1SW terminal and CP2SW happen, the internal elements are protected with the abnormality detection circuits. The details are shown in chapter 7.6.8.
Fig. 7.1 Charge Pump Circuit Block Diagram
© 2 025 6 2025-07-31 Toshiba Electronic Devices & Storage Corporation Rev. 3.0 Document Outline 1. Description 2. Applications 3. Features 4. Block Diagram 5. Pin Assignments Top view 6. Pin Description 7. Functional Description 7.1. Charge Pump Circuit 7.2. Gate Driver Circuits 7.2.1. Gate Drivers for Driving 3-Phase FETs 7.2.2. Gate Driver for FET for Reverse Polarity Protection 7.3. Current Sensing Circuit 7.3.1. Configuration 7.3.2. Offset Calibration 7.4. Oscillation Circuit 7.5. Abnormality Flag Output Function 7.5.1. NDIAG Terminal Output 7.5.2. Status Registers in SPI communication 7.6. Abnormality Detection Circuits 7.6.1. VCC Under Voltage Detection Function 7.6.2. VB Under Voltage Detection Function 7.6.3. RPPO Under Voltage Detection Function 7.6.4. VCC Over Voltage Detection Function 7.6.5. VCP Over Voltage Detection Function 7.6.6. Over temperature Detection Function 7.6.7. VDS Detection Function for 3-Phase FETs 7.6.8. Abnormality Detection for CP1SW and CP2SW Terminals 7.7. Alarm Input Circuit 7.8. SPI Communication Circuit 7.8.1. SPI Communication Operation 7.8.2. Error Judgment 7.8.3. Register Map 7.8.3.1. CONFIG1 Write Address=2h / Read Address=3h 7.8.3.2. CONFIG2 Write Address=4h / Read Address=5h 7.8.3.3. CONFIG3 Write Address=6h / Read Address=7h 7.8.3.4. CONFIG4 (Write Address=8h / Read Address=9h 7.8.3.5. CONFIG5 Write Address=Ah / Read Address=Bh 7.8.3.6. STAT1 / Read Address=Dh 7.8.3.7. STAT2 / Read Address=Fh 7.8.3.8. STAT1_CLR Write Address=10h 7.8.3.9. STAT2_CLR Write Address=12h 7.8.3.10. NOP Write Address=Fh / Read Address=Fh 8. Absolute Maximum Ratings (Ta = 25 C) 9. Electrical Characteristics 9.1. Operating Voltage Ranges 9.2. Consumption Current 9.3. Charge Pump Circuit 9.4. Gate Driver Circuits 9.5. Current Sense Amplifier Circuit 9.6. Oscillation Circuit 9.7. Abnormality Detection Circuits 9.8. Alarm Input Circuit 9.9. SPI Communication Circuit 10. Application Circuit Example 11. Package Outlines 12. Revision History 13. Abbreviation Collection RESTRICTIONS ON PRODUCT USE