Datasheet OPA186 (Texas Instruments) - 9
| 制造商 | Texas Instruments |
| 描述 | Single, 24-V, low-power (90 μA) 5-μV-offset zero-drift op amp with rail-to-rail input and o |
| 页数 / 页 | 49 / 9 — OPA186. , OPA2186. , OPA4186. www.ti.com. 6.8 Typical Characteristics. … |
| 文件格式/大小 | PDF / 2.6 Mb |
| 文件语言 | 英语 |
OPA186. , OPA2186. , OPA4186. www.ti.com. 6.8 Typical Characteristics. Table 6-1. Typical Characteristic Graphs. DESCRIPTION. FIGURE
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OPA186 , OPA2186 , OPA4186 www.ti.com
SBOS968C – JUNE 2022 – REVISED JULY 2023
6.8 Typical Characteristics
at TA = 25°C, VS = ±12 V, VCM = VS / 2, RL = 10 kΩ (unless otherwise noted)
Table 6-1. Typical Characteristic Graphs DESCRIPTION FIGURE
Offset Voltage Distribution Figure 6-1 Offset Voltage Drift (-40°C to +125C°C) Figure 6-2 Input Bias Current Distribution Figure 6-3 Input Offset Current Distribution Figure 6-4 Offset Voltage vs Common-Mode Voltage Figure 6-5 Offset Voltage vs Supply Voltage Figure 6-6 Input Bias Current vs Common-Mode Voltage Figure 6-7 Open-Loop Gain and Phase vs Frequency Figure 6-8 Closed-Loop Gain vs Frequency Figure 6-9 Input Bias Current and Offset Current vs Temperature Figure 6-10 Output Voltage Swing vs Output Current (Sourcing) Figure 6-11 Output Voltage Swing vs Output Current (Sinking) Figure 6-12 CMRR and PSRR vs Frequency Figure 6-13 CMRR vs Temperature Figure 6-14 PSRR vs Temperature Figure 6-15 0.1-Hz to 10-Hz Voltage Noise Figure 6-16 Input Voltage Noise Spectral Density vs Frequency Figure 6-17 THD+N vs Frequency Figure 6-18 THD+N vs Output Amplitude Figure 6-19 Quiescent Current vs Supply Voltage Figure 6-20 Quiescent Current vs Temperature Figure 6-21 Open-Loop Gain vs Temperature (10 kΩ) Figure 6-22 Open-Loop Gain vs Temperature (2 kΩ) Figure 6-23 Open-Loop Output Impedance vs Frequency Figure 6-24 Small-Signal Overshoot vs Capacitive Load (Gain = –1, 10-mV step) Figure 6-25 Small-Signal Overshoot vs Capacitive Load (Gain = 1, 10-mV step) Figure 6-26 No Phase Reversal Figure 6-27 Positive Overload Recovery Figure 6-28 Negative Overload Recovery Figure 6-29 Small-Signal Step Response (Gain = 1, 10-mV step) Figure 6-30 Small-Signal Step Response (Gain = –1, 10-mV step) Figure 6-31 Large-Signal Step Response (Gain = 1, 10-V step) Figure 6-32 Large-Signal Step Response (Gain = –1, 10-V step) Figure 6-33 Phase Margin vs Capacitive Load Figure 6-34 Settling Time (1-V Step, 0.1% Settling) Figure 6-35 Short Circuit Current vs Temperature Figure 6-36 Maximum Output Voltage vs Frequency Figure 6-37 EMIRR vs Frequency Figure 6-38 Channel Separation Figure 6-39 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: OPA186 OPA2186 OPA4186 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information: OPA186 6.5 Thermal Information: OPA2186 6.6 Thermal Information: OPA4186 6.7 Electrical Characteristics 6.8 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Rail-to-Rail Inputs 7.3.2 Phase-Reversal Protection 7.3.3 Input Bias Current Clock Feedthrough 7.3.4 EMI Rejection 7.3.4.1 EMIRR +IN Test Configuration 7.3.5 Electrical Overstress 7.3.6 MUX-Friendly Inputs 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.1.1 Basic Noise Calculations 8.2 Typical Applications 8.2.1 High-Side Current Sensing 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.3 Application Curve 8.2.2 Bridge Amplifier 8.3 Power Supply Recommendations 8.4 Layout 8.4.1 Layout Guidelines 8.4.2 Layout Example 9 Device and Documentation Support 9.1 Device Support 9.1.1 Development Support 9.1.1.1 PSpice® for TI 9.1.1.2 TINA-TI™ Simulation Software (Free Download) 9.2 Documentation Support 9.2.1 Related Documentation 9.3 Receiving Notification of Documentation Updates 9.4 Support Resources 9.5 Trademarks 9.6 Electrostatic Discharge Caution 9.7 Glossary 10 Mechanical, Packaging, and Orderable Information
OPA186 , OPA2186 , OPA4186 www.ti.com
SBOS968C – JUNE 2022 – REVISED JULY 2023
6.8 Typical Characteristics
at TA = 25°C, VS = ±12 V, VCM = VS / 2, RL = 10 kΩ (unless otherwise noted)
Table 6-1. Typical Characteristic Graphs DESCRIPTION FIGURE
Offset Voltage Distribution Figure 6-1 Offset Voltage Drift (-40°C to +125C°C) Figure 6-2 Input Bias Current Distribution Figure 6-3 Input Offset Current Distribution Figure 6-4 Offset Voltage vs Common-Mode Voltage Figure 6-5 Offset Voltage vs Supply Voltage Figure 6-6 Input Bias Current vs Common-Mode Voltage Figure 6-7 Open-Loop Gain and Phase vs Frequency Figure 6-8 Closed-Loop Gain vs Frequency Figure 6-9 Input Bias Current and Offset Current vs Temperature Figure 6-10 Output Voltage Swing vs Output Current (Sourcing) Figure 6-11 Output Voltage Swing vs Output Current (Sinking) Figure 6-12 CMRR and PSRR vs Frequency Figure 6-13 CMRR vs Temperature Figure 6-14 PSRR vs Temperature Figure 6-15 0.1-Hz to 10-Hz Voltage Noise Figure 6-16 Input Voltage Noise Spectral Density vs Frequency Figure 6-17 THD+N vs Frequency Figure 6-18 THD+N vs Output Amplitude Figure 6-19 Quiescent Current vs Supply Voltage Figure 6-20 Quiescent Current vs Temperature Figure 6-21 Open-Loop Gain vs Temperature (10 kΩ) Figure 6-22 Open-Loop Gain vs Temperature (2 kΩ) Figure 6-23 Open-Loop Output Impedance vs Frequency Figure 6-24 Small-Signal Overshoot vs Capacitive Load (Gain = –1, 10-mV step) Figure 6-25 Small-Signal Overshoot vs Capacitive Load (Gain = 1, 10-mV step) Figure 6-26 No Phase Reversal Figure 6-27 Positive Overload Recovery Figure 6-28 Negative Overload Recovery Figure 6-29 Small-Signal Step Response (Gain = 1, 10-mV step) Figure 6-30 Small-Signal Step Response (Gain = –1, 10-mV step) Figure 6-31 Large-Signal Step Response (Gain = 1, 10-V step) Figure 6-32 Large-Signal Step Response (Gain = –1, 10-V step) Figure 6-33 Phase Margin vs Capacitive Load Figure 6-34 Settling Time (1-V Step, 0.1% Settling) Figure 6-35 Short Circuit Current vs Temperature Figure 6-36 Maximum Output Voltage vs Frequency Figure 6-37 EMIRR vs Frequency Figure 6-38 Channel Separation Figure 6-39 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: OPA186 OPA2186 OPA4186 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information: OPA186 6.5 Thermal Information: OPA2186 6.6 Thermal Information: OPA4186 6.7 Electrical Characteristics 6.8 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Rail-to-Rail Inputs 7.3.2 Phase-Reversal Protection 7.3.3 Input Bias Current Clock Feedthrough 7.3.4 EMI Rejection 7.3.4.1 EMIRR +IN Test Configuration 7.3.5 Electrical Overstress 7.3.6 MUX-Friendly Inputs 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.1.1 Basic Noise Calculations 8.2 Typical Applications 8.2.1 High-Side Current Sensing 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.3 Application Curve 8.2.2 Bridge Amplifier 8.3 Power Supply Recommendations 8.4 Layout 8.4.1 Layout Guidelines 8.4.2 Layout Example 9 Device and Documentation Support 9.1 Device Support 9.1.1 Development Support 9.1.1.1 PSpice® for TI 9.1.1.2 TINA-TI™ Simulation Software (Free Download) 9.2 Documentation Support 9.2.1 Related Documentation 9.3 Receiving Notification of Documentation Updates 9.4 Support Resources 9.5 Trademarks 9.6 Electrostatic Discharge Caution 9.7 Glossary 10 Mechanical, Packaging, and Orderable Information