Datasheet OPA186 (Texas Instruments) - 3
| 制造商 | Texas Instruments |
| 描述 | Single, 24-V, low-power (90 μA) 5-μV-offset zero-drift op amp with rail-to-rail input and o |
| 页数 / 页 | 49 / 3 — OPA186. , OPA2186. , OPA4186. www.ti.com. 5 Pin Configuration and … |
| 文件格式/大小 | PDF / 2.6 Mb |
| 文件语言 | 英语 |
OPA186. , OPA2186. , OPA4186. www.ti.com. 5 Pin Configuration and Functions. Figure 5-1. OPA186: D Package, 8-Pin SOIC
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OPA186 , OPA2186 , OPA4186 www.ti.com
SBOS968C – JUNE 2022 – REVISED JULY 2023
5 Pin Configuration and Functions
NC 1 8 NC OUT 1 5 V+ 2 ±IN ± 7 V+ V 2 ± +IN 3 + 6 OUT + ± +IN 3 4 V 4 ± 5 NC ±IN Not to scale Not to scale
Figure 5-1. OPA186: D Package, 8-Pin SOIC Figure 5-2. OPA186: DBV Package, 5-Pin SOT-23 (Top View) (Top View) Table 5-1. Pin Functions: OPA186 PIN NO. TYPE DESCRIPTION NAME D (SOIC) DBV (SOT-23)
–IN 4 2 Input Inverting input +IN 3 3 Input Noninverting input OUT 1 6 Output Output V– 2 4 Power Negative (lowest) power supply V+ 5 7 Power Positive (highest) power supply NC — 1, 8, 5 — No connection (can be left floating) OUT A 1 8 V+ 2 ±IN A 7 OUT B +IN A 3 6 ±IN B V 4 ± 5 +IN B Not to scale
Figure 5-3. OPA2186: D Package, 8-Pin SOIC and DDF Package, 8-Pin SOT-23 (Top View) Table 5-2. Pin Functions: OPA2186 PIN TYPE DESCRIPTION NAME NO.
–IN A 2 Input Inverting input channel A +IN A 3 Input Noninverting input channel A –IN B 6 Input Inverting input channel B +IN B 5 Input Noninverting input channel B OUT A 1 Output Output channel A OUT B 7 Output Output channel B V– 4 Power Negative supply V+ 8 Power Positive supply Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: OPA186 OPA2186 OPA4186 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information: OPA186 6.5 Thermal Information: OPA2186 6.6 Thermal Information: OPA4186 6.7 Electrical Characteristics 6.8 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Rail-to-Rail Inputs 7.3.2 Phase-Reversal Protection 7.3.3 Input Bias Current Clock Feedthrough 7.3.4 EMI Rejection 7.3.4.1 EMIRR +IN Test Configuration 7.3.5 Electrical Overstress 7.3.6 MUX-Friendly Inputs 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.1.1 Basic Noise Calculations 8.2 Typical Applications 8.2.1 High-Side Current Sensing 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.3 Application Curve 8.2.2 Bridge Amplifier 8.3 Power Supply Recommendations 8.4 Layout 8.4.1 Layout Guidelines 8.4.2 Layout Example 9 Device and Documentation Support 9.1 Device Support 9.1.1 Development Support 9.1.1.1 PSpice® for TI 9.1.1.2 TINA-TI™ Simulation Software (Free Download) 9.2 Documentation Support 9.2.1 Related Documentation 9.3 Receiving Notification of Documentation Updates 9.4 Support Resources 9.5 Trademarks 9.6 Electrostatic Discharge Caution 9.7 Glossary 10 Mechanical, Packaging, and Orderable Information
SBOS968C – JUNE 2022 – REVISED JULY 2023
5 Pin Configuration and Functions
NC 1 8 NC OUT 1 5 V+ 2 ±IN ± 7 V+ V 2 ± +IN 3 + 6 OUT + ± +IN 3 4 V 4 ± 5 NC ±IN Not to scale Not to scale
Figure 5-1. OPA186: D Package, 8-Pin SOIC Figure 5-2. OPA186: DBV Package, 5-Pin SOT-23 (Top View) (Top View) Table 5-1. Pin Functions: OPA186 PIN NO. TYPE DESCRIPTION NAME D (SOIC) DBV (SOT-23)
–IN 4 2 Input Inverting input +IN 3 3 Input Noninverting input OUT 1 6 Output Output V– 2 4 Power Negative (lowest) power supply V+ 5 7 Power Positive (highest) power supply NC — 1, 8, 5 — No connection (can be left floating) OUT A 1 8 V+ 2 ±IN A 7 OUT B +IN A 3 6 ±IN B V 4 ± 5 +IN B Not to scale
Figure 5-3. OPA2186: D Package, 8-Pin SOIC and DDF Package, 8-Pin SOT-23 (Top View) Table 5-2. Pin Functions: OPA2186 PIN TYPE DESCRIPTION NAME NO.
–IN A 2 Input Inverting input channel A +IN A 3 Input Noninverting input channel A –IN B 6 Input Inverting input channel B +IN B 5 Input Noninverting input channel B OUT A 1 Output Output channel A OUT B 7 Output Output channel B V– 4 Power Negative supply V+ 8 Power Positive supply Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: OPA186 OPA2186 OPA4186 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information: OPA186 6.5 Thermal Information: OPA2186 6.6 Thermal Information: OPA4186 6.7 Electrical Characteristics 6.8 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Rail-to-Rail Inputs 7.3.2 Phase-Reversal Protection 7.3.3 Input Bias Current Clock Feedthrough 7.3.4 EMI Rejection 7.3.4.1 EMIRR +IN Test Configuration 7.3.5 Electrical Overstress 7.3.6 MUX-Friendly Inputs 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.1.1 Basic Noise Calculations 8.2 Typical Applications 8.2.1 High-Side Current Sensing 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.3 Application Curve 8.2.2 Bridge Amplifier 8.3 Power Supply Recommendations 8.4 Layout 8.4.1 Layout Guidelines 8.4.2 Layout Example 9 Device and Documentation Support 9.1 Device Support 9.1.1 Development Support 9.1.1.1 PSpice® for TI 9.1.1.2 TINA-TI™ Simulation Software (Free Download) 9.2 Documentation Support 9.2.1 Related Documentation 9.3 Receiving Notification of Documentation Updates 9.4 Support Resources 9.5 Trademarks 9.6 Electrostatic Discharge Caution 9.7 Glossary 10 Mechanical, Packaging, and Orderable Information