Datasheet MAX32625 (Analog Devices) - 6

MAX32625/MAX32626 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 512KB Flash and 160KB SRAM
Electrical Characteristics
(Limits are 100% tested at TA = +25ºC and TA = +85ºC. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to -30°C are guaranteed by design and are not production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLIES
VDD18 1.71 1.8 1.89 VDD12 1.14 1.2 1.26 Supply Voltage VRTC 1.75 1.8 1.89 V VDDIO 1.71 1.8 3.6 VDDIOH VDDIOH must be ≥ VDDIO 1.71 1.8 3.6 1.2V Internal Regulator VREG12 1.14 1.2 1.26 V Power-Fail Reset Voltage VRST Monitors VDD18 1.61 1.7 V Power-On Reset Voltage VPOR Monitors VDD18 1.5 V RAM Data Retention Voltage VDRV VDD12 supply, retention in LP1 0.930 mV Measured on the VDD12 pin and execut- VDD12 Dynamic ing code from cache memory, all inputs Current, LP3 Mode IDD12_DLP3 are tied to V 106 μA/MHz SS or VDD18, outputs do not source/sink any current, PMU disabled 96MHz oscillator selected as system clock, measured on the VDD12 pin and execut- ing code from cache memory, all inputs 87 are tied to VSS or VDD18, outputs do not VDD12 Fixed Current, LP3 source/sink any current Mode IDD12_FLP3 μA 4MHz oscillator selected as system clock, measured on the VDD12 pin and execut- ing code from cache memory, all inputs 39 are tied to VSS or VDD18, outputs do not source/sink any current 96MHz oscillator selected as system clock, measured on the VDD18 pin and execut- ing code from cache memory, all inputs 366 are tied to VSS or VDD18, outputs do not VDD18 Fixed Current, LP3 source/sink any current Mode IDD18_FLP3 μA 4MHz oscillator selected as system clock, measured on the VDD18 pin and execut- ing code from cache memory, all inputs 33 are tied to VSS or VDD18, outputs do not source/sink any current VDD12 Dynamic Measured on the VDD12 pin, ARM in sleep Current, LP2 Mode IDD12_DLP2 mode, PMU with two channels active 27 μA/MHz www.maximintegrated.com Maxim Integrated │ 6 Document Outline General Description Applications Benefits and Features Simplified Block Diagram Absolute Maximum Ratings Package Information 63 WLP 68 TQFN Electrical Characteristics Electrical Characteristics - ADC Electrical Characteristics - USB Electrical Characteristics - SPI Master / SPIX Master Electrical Characteristics - SPI Slave Electrical Characteristics - I2C Bus Pin Configurations Pin Description Detailed Description MAX32625/MAX32626 ARM Cortex-M4 with FPU Processor Power Operating Modes Low Power Mode 0 (LP0) Low Power Mode 1 (LP1) Low Power Mode 2 (LP2) Low Power Mode 3 (LP3) Analog-to-Digital Converter Pulse Train Engine Clocking Scheme Interrupt Sources Real-Time Clock and Wake-Up Timer General-Purpose I/O and Special Function Pins CRC Module Watchdog Timers Programmable Timers Serial Peripherals USB I2C Master and Slave SPI (Master) SPI (Slave) SPI (Execute in Place (SPIX) Master) UART 1-Wire Master Peripheral Management Unit (PMU) Additional Documentation Development and Technical Support Trust Protection Unit (TPU) (MAX32626 Only) Applications Information General-Purpose I/O Matrix Typical Application Circuit Ordering Information Revision History