Datasheet MAX32625 (Analog Devices) - 5

MAX32625/MAX32626 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 512KB Flash and 160KB SRAM
Absolute Maximum Ratings
VDD18 ...-0.3V to +1.89V Total Current into All VDDIO and VDDIOH VDD12 ...-0.3V to +1.32V Power Pins Combined (Sink) ...100mA VRTC ...-0.3V to +1.89V Total Current into VSS ..100mA VDDB ..-0.3V to +3.6V Output Current (Sink) by Any I/O Pin ...25mA VDDIO ...-0.3V to +3.6V Output Current (Source) by Any I/O Pin..-25mA VDDIOH ...-0.3V to +3.6V Continuous Package Power Dissipation TQFN (multilayer board) 32KIN, 32KOUT..-0.3V to +3.6V TA = +70°C (derate 49.5mW/°C above +70°C) ..3960.4mW RSTN, SRSTN, DP, DM, GPIO, JTAG ...-0.3V to +3.6V Operating Temperature Range ... -30°C to +85°C AIN[1:0]...-0.3V to +5.5V Storage Temperature Range .. -65°C to +150°C AIN[3:2]...-0.3V to +3.6V Soldering Temperature (reflow) ...+260°C (All voltages with respect to VSS, unless otherwise noted.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Package Information 63 WLP PACKAGE CODE W6333B+1
Outline Number
21-100084
Land Pattern Number Refer to
Application Note 1891 Thermal Resistance, Single Layer Board:
Junction-to-Ambient (θJA) N/A Junction-to-Case Thermal Resistance (θJC) N/A
Thermal Resistance, Four Layer Board:
Junction-to-Ambient (θJA) 35.87 ºC/W Junction-to-Case Thermal Resistance (θJC) N/A
68 TQFN-EP PACKAGE CODE T6888+1
Outline Number
21-0510
Land Pattern Number
90-0354 Thermal Resistance, Single Layer Board:
Junction-to-Ambient (θJA) N/A Junction-to-Case Thermal Resistance (θJC) N/A
Thermal Resistance, Four Layer Board:
Junction-to-Ambient (θJA) 20.20ºC/W Junction-to-Case Thermal Resistance (θJC) 1ºC/W For the latest package outline information and land patterns (footprints), go to
www.maximintegrated.com/packaging
. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial
. www.maximintegrated.com Maxim Integrated │ 5 Document Outline General Description Applications Benefits and Features Simplified Block Diagram Absolute Maximum Ratings Package Information 63 WLP 68 TQFN Electrical Characteristics Electrical Characteristics - ADC Electrical Characteristics - USB Electrical Characteristics - SPI Master / SPIX Master Electrical Characteristics - SPI Slave Electrical Characteristics - I2C Bus Pin Configurations Pin Description Detailed Description MAX32625/MAX32626 ARM Cortex-M4 with FPU Processor Power Operating Modes Low Power Mode 0 (LP0) Low Power Mode 1 (LP1) Low Power Mode 2 (LP2) Low Power Mode 3 (LP3) Analog-to-Digital Converter Pulse Train Engine Clocking Scheme Interrupt Sources Real-Time Clock and Wake-Up Timer General-Purpose I/O and Special Function Pins CRC Module Watchdog Timers Programmable Timers Serial Peripherals USB I2C Master and Slave SPI (Master) SPI (Slave) SPI (Execute in Place (SPIX) Master) UART 1-Wire Master Peripheral Management Unit (PMU) Additional Documentation Development and Technical Support Trust Protection Unit (TPU) (MAX32626 Only) Applications Information General-Purpose I/O Matrix Typical Application Circuit Ordering Information Revision History