Databrief PIC18-Q71 (Microchip) - 3
| 制造商 | Microchip |
| 描述 | PIC18-Q71 Family Product Brief |
| 页数 / 页 | 18 / 3 — PIC18-Q71. Power-Saving Functionality. Digital Peripherals. Product Brief |
| 文件格式/大小 | PDF / 249 Kb |
| 文件语言 | 英语 |
PIC18-Q71. Power-Saving Functionality. Digital Peripherals. Product Brief
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PIC18-Q71
– 1.8V to 5.5V • Temperature Range: – Industrial: -40°C to 85°C – Extended: -40°C to 125°C
Power-Saving Functionality
• Doze: CPU and Peripherals Running at Different Cycle Rates (CPU is typically slower) • Idle: CPU Halted While Peripherals Operate • Sleep: Lowest Power Consumption • Peripheral Module Disable (PMD): – Ability to selectively disable hardware module to minimize active power consumption of unused peripherals • Analog Peripheral Manager: – Can be used to optimize power consumption in applications that use analog peripherals by switching them on and off as needed, core independently using dedicated timer resources • Low-Power Mode Features: – Sleep: < 1 µA typical @ 3V – Operating Current: • 48 µA @ 32 kHz, 3V, typical
Digital Peripherals
• Three 16-Bit Pulse-Width Modulators (PWM): – Dual outputs for each PWM module – Integrated 16-bit timer/counter – Double-buffered user registers for duty cycles – Right/Left/Center/Variable-aligned modes of operation – Multiple clock and Reset signal selections • Three 16-Bit Timers (TMR0/1/3) • Two 8-Bit Timers (TMR2/4) with Hardware Limit Timer (HLT) • Two Universal Timers (TMRU16A/16B): – New Timer modules with features of TMR0/TMR1/TMR2 (Gate, Hardware Limit) – Two 16-bit timers can be chained together to create a combined 32-bit timer • Eight Configurable Logic Cells (CLC): – Integrated combinational and sequential logic • One Complimentary Waveform Generator (CWG): – Rising and falling edge dead-band control – Full-bridge, half-bridge, one-channel drive – Multiple signal sources – Programmable dead band – Fault-shutdown input • Two Capture/Compare/PWM (CCP) Modules: – 16-bit resolution for Capture/Compare modes – 10-bit resolution for PWM mode • One Numerically Controlled Oscillator (NCO): – Generates true linear frequency control and increased frequency resolution – Input clock up to 64 MHz • Programmable CRC with Memory Scan: – Reliable data/program memory monitoring for Fail-Safe operation (e.g., Class B) – Calculate 32-bit CRC over any portion of Program Flash Memory © 2021 Microchip Technology Inc.
Product Brief
DS40002289A-page 3 Document Outline Introduction PIC18-Q71 Family Types Features Memory Operating Characteristics Power-Saving Functionality Digital Peripherals Analog Peripherals Clocking Structure Programming/Debug Features 1. Packages 2. Pin Diagrams 3. Pin Allocation Tables The Microchip Website Product Change Notification Service Customer Support Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service
– 1.8V to 5.5V • Temperature Range: – Industrial: -40°C to 85°C – Extended: -40°C to 125°C
Power-Saving Functionality
• Doze: CPU and Peripherals Running at Different Cycle Rates (CPU is typically slower) • Idle: CPU Halted While Peripherals Operate • Sleep: Lowest Power Consumption • Peripheral Module Disable (PMD): – Ability to selectively disable hardware module to minimize active power consumption of unused peripherals • Analog Peripheral Manager: – Can be used to optimize power consumption in applications that use analog peripherals by switching them on and off as needed, core independently using dedicated timer resources • Low-Power Mode Features: – Sleep: < 1 µA typical @ 3V – Operating Current: • 48 µA @ 32 kHz, 3V, typical
Digital Peripherals
• Three 16-Bit Pulse-Width Modulators (PWM): – Dual outputs for each PWM module – Integrated 16-bit timer/counter – Double-buffered user registers for duty cycles – Right/Left/Center/Variable-aligned modes of operation – Multiple clock and Reset signal selections • Three 16-Bit Timers (TMR0/1/3) • Two 8-Bit Timers (TMR2/4) with Hardware Limit Timer (HLT) • Two Universal Timers (TMRU16A/16B): – New Timer modules with features of TMR0/TMR1/TMR2 (Gate, Hardware Limit) – Two 16-bit timers can be chained together to create a combined 32-bit timer • Eight Configurable Logic Cells (CLC): – Integrated combinational and sequential logic • One Complimentary Waveform Generator (CWG): – Rising and falling edge dead-band control – Full-bridge, half-bridge, one-channel drive – Multiple signal sources – Programmable dead band – Fault-shutdown input • Two Capture/Compare/PWM (CCP) Modules: – 16-bit resolution for Capture/Compare modes – 10-bit resolution for PWM mode • One Numerically Controlled Oscillator (NCO): – Generates true linear frequency control and increased frequency resolution – Input clock up to 64 MHz • Programmable CRC with Memory Scan: – Reliable data/program memory monitoring for Fail-Safe operation (e.g., Class B) – Calculate 32-bit CRC over any portion of Program Flash Memory © 2021 Microchip Technology Inc.
Product Brief
DS40002289A-page 3 Document Outline Introduction PIC18-Q71 Family Types Features Memory Operating Characteristics Power-Saving Functionality Digital Peripherals Analog Peripherals Clocking Structure Programming/Debug Features 1. Packages 2. Pin Diagrams 3. Pin Allocation Tables The Microchip Website Product Change Notification Service Customer Support Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service