Datasheet RAA788150, RAA788152, RAA788153, RAA788155, RAA788156, RAA788158 (Renesas) - 3
| 制造商 | Renesas |
| 描述 | Large 3V Output Swing, 5kV EFT, 16.5kV ESD, RS-485 Transceivers |
| 页数 / 页 | 34 / 3 — RAA788150, RAA788152, RAA788153, RAA788155, RAA788156, RAA788158 … |
| 文件格式/大小 | PDF / 613 Kb |
| 文件语言 | 英语 |
RAA788150, RAA788152, RAA788153, RAA788155, RAA788156, RAA788158 Datasheet. 1. Overview. 1.1. Typical Operating Circuit
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RAA788150, RAA788152, RAA788153, RAA788155, RAA788156, RAA788158 Datasheet 1. Overview 1.1 Typical Operating Circuit
5V 100n 5V 100 n VCC 10k VCC 10k RO A
R
A/Y RO
R
RT RE B RL78 RE DE RT RL78 MCU B/Z DE MCU DI Y
D
DI
D
Z 10k 10k GND 10k 10k GND
Figure 2. Typical Operating Circuits of Half-Duplex and Full-Duplex Transceivers 2. Pin Information 2.1 Pin Assignments
RAA788152, RAA788155, RAA788158 RAA788150, RAA788153, RAA788156 RAA788150, RAA788153, RAA788156 (8 Ld MSOP, 8 Ld SOIC) (10 Ld MSOP) (14 Ld SOIC) Top View Top View Top View
RO 1 R 8 VCC RO 1 R 10 VCC NC 1 14 VCC RE 2 7 B/Z RE 2 9 A RO 2 R 13 NC DE 3 6 A/Y DE 3 8 B RE 3 12 A DI 4 D 5 GND DI 4 D 7 Z DE 4 11 B GND 5 6 Y DI 5 D 10 Z GND 6 9 Y GND 7 8 NC
R15DS0005EU0102 Rev.1.02 Page 3 Aug 19, 2021 Document Outline Features Applications Contents 1. Overview 1.1 Typical Operating Circuit 2. Pin Information 2.1 Pin Assignments 2.2 Pin Descriptions 3. Specifications 3.1 Absolute Maximum Ratings 3.2 Recommended Operating Conditions 3.3 Thermal Information 3.4 Electrical Specifications 4. Test Circuits and Waveforms 5. Typical Performance Curves 6. Device Description 6.1 Overview 6.2 Functional Block Diagram 6.3 Operating Modes 6.3.1 Driver Operation 6.3.2 Receiver Operation 6.4 Device Features 6.4.1 Large Output Signal Swing 6.4.2 Driver Overload Protection 6.4.3 Full-Failsafe Receiver 6.4.4 Low Current Shutdown Mode 6.4.5 Hot Plug Function 6.4.6 High EFT Immunity 6.4.7 High ESD Protection 7. Application Information 7.1 Network Design 7.1.1 Cable Type 7.1.2 Cable Length vs Data Rate 7.1.3 Topologies and Stub Lengths 7.1.4 Minimum Distance between Nodes 7.1.5 Failsafe Biasing Termination 7.2 Transient Protection 7.3 Layout Guidelines 7.3.1 Layout Example 8. Package Outline Drawings 9. Ordering Information 10. Revision History
5V 100n 5V 100 n VCC 10k VCC 10k RO A
R
A/Y RO
R
RT RE B RL78 RE DE RT RL78 MCU B/Z DE MCU DI Y
D
DI
D
Z 10k 10k GND 10k 10k GND
Figure 2. Typical Operating Circuits of Half-Duplex and Full-Duplex Transceivers 2. Pin Information 2.1 Pin Assignments
RAA788152, RAA788155, RAA788158 RAA788150, RAA788153, RAA788156 RAA788150, RAA788153, RAA788156 (8 Ld MSOP, 8 Ld SOIC) (10 Ld MSOP) (14 Ld SOIC) Top View Top View Top View
RO 1 R 8 VCC RO 1 R 10 VCC NC 1 14 VCC RE 2 7 B/Z RE 2 9 A RO 2 R 13 NC DE 3 6 A/Y DE 3 8 B RE 3 12 A DI 4 D 5 GND DI 4 D 7 Z DE 4 11 B GND 5 6 Y DI 5 D 10 Z GND 6 9 Y GND 7 8 NC
R15DS0005EU0102 Rev.1.02 Page 3 Aug 19, 2021 Document Outline Features Applications Contents 1. Overview 1.1 Typical Operating Circuit 2. Pin Information 2.1 Pin Assignments 2.2 Pin Descriptions 3. Specifications 3.1 Absolute Maximum Ratings 3.2 Recommended Operating Conditions 3.3 Thermal Information 3.4 Electrical Specifications 4. Test Circuits and Waveforms 5. Typical Performance Curves 6. Device Description 6.1 Overview 6.2 Functional Block Diagram 6.3 Operating Modes 6.3.1 Driver Operation 6.3.2 Receiver Operation 6.4 Device Features 6.4.1 Large Output Signal Swing 6.4.2 Driver Overload Protection 6.4.3 Full-Failsafe Receiver 6.4.4 Low Current Shutdown Mode 6.4.5 Hot Plug Function 6.4.6 High EFT Immunity 6.4.7 High ESD Protection 7. Application Information 7.1 Network Design 7.1.1 Cable Type 7.1.2 Cable Length vs Data Rate 7.1.3 Topologies and Stub Lengths 7.1.4 Minimum Distance between Nodes 7.1.5 Failsafe Biasing Termination 7.2 Transient Protection 7.3 Layout Guidelines 7.3.1 Layout Example 8. Package Outline Drawings 9. Ordering Information 10. Revision History