Datasheet SiC450, SiC451, SiC453 (Vishay) - 7
| 制造商 | Vishay |
| 描述 | 4.5 V to 20 V Input, 15 A, 25 A, 40 A microBuck DC/DC Converter With PMBus Interface |
| 页数 / 页 | 48 / 7 — SiC450, SiC451, SiC453. OPERATIONAL DESCRIPTION Device Overview. Fig. 5 - … |
| 文件格式/大小 | PDF / 1.3 Mb |
| 文件语言 | 英语 |
SiC450, SiC451, SiC453. OPERATIONAL DESCRIPTION Device Overview. Fig. 5 - VM-COT Block Diagram. PWM Control Mechanism
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SiC450, SiC451, SiC453
www.vishay.com Vishay Siliconix
OPERATIONAL DESCRIPTION Device Overview
SiC45x is a high efficiency synchronous buck regulator PVIN capable of delivering up to 25 A continuous current. The PVIN device has programmable switching frequency of 300 kHz to 1.5 MHz. The control scheme delivers fast transient SW response and minimizes external components. Thanks to the internal current ramp information, no high ESR output Load PGND bulk or virtual ESR network is required for the loop stability. Constant on time This device also incorporates a power saving feature by PWM generator enabling diode emulation mode and frequency fold back as the load decreases. V Ramp generator SEN+ Comparator Differential In addition, a built in PLL allows in phase or 180° out of amplifier OTA phase synchronization under master / slave configuration. V REF SEN- C R P comp SiC45x has a full set of protection and monitoring features Ccomp with response that can be set with PMBus: AGND • Over current protection in pulse-by-pulse mode
Fig. 5 - VM-COT Block Diagram
• Output over voltage protection All components for RAMP signal generation and error • Output under voltage protection amplifier compensation required for the control loop are • Over temperature protection with hysteresis internal to the IC, see Fig. 5. In order for the device to cover • Dedicated enable pin for easy power sequencing a wide range of VOUT operation, the internal RAMP signal • Power good open drain output components are automatically selected depending on the V This device is available in MLP34-57 package to deliver high OUT voltage and switching frequency. The error amplifier internal compensation consists of a resistor in series with a power density and minimize PCB area. capacitor (RCOMP, CCOMP).
PWM Control Mechanism
Fig. 6 demonstrates the basic operational waveforms: SiC45x employs a voltage - mode COT control mechanism. During steady-state operation, feedback voltage is Basic operational waveforms compared with internal reference and the amplified error signal (VCOMP) is generated in the internal comp node. An internally generated ramp signal and V V COMP are fed into a RAMP comparator. Once VRAMP crosses VCOMP, a single shot on-time pulse is generated for a fixed time, programmed by the external Rfsw. During the on-time pulse, the high side MOSFET will be turned on. Once the on-time pulse expires, VCOMP the low side MOSFET will be turned on after a break-before-make period. The low side MOSFET will be on for duration of minimum off-time pulse until VRAMP crosses VCOMP. The cycle is then repeated. Fig. 5 illustrates the basic block diagram for VM-COT architecture. In this architecture the following is achieved: PWM Fixed on-time • The reference of a basic ripple control regulator is
Fig. 6 - VM-COT Operational Principle
replaced with a high again error amplifier loop
Light Load Condition
• This establishes two parallel voltage regulating feedback To improve efficiency at light-load condition, SiC45x paths, a fast and slow path provide a set of innovative implementations to eliminate LS • Fast path is the ripple injection which ensures rapid recirculating current and switching losses. The internal zero correction of the transient perturbation crossing detector monitors SW node voltage to determine • Slow path is the error amplifier loop which ensures the DC when inductor current starts to flow negatively. In power component of the output voltage follows the internal saving mode, as soon as inductor valley current crosses accurate reference voltage zero, the device deploys diode emulation mode by turning off low side MOSFET. If load further decreases, switching frequency is reduced proportional to load condition to save switching losses while keeping output ripple within tolerance. The switching frequency is set by the controller to S21-0213-Rev. B, 08-Mar-2021
7
Document Number: 77863 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
www.vishay.com Vishay Siliconix
OPERATIONAL DESCRIPTION Device Overview
SiC45x is a high efficiency synchronous buck regulator PVIN capable of delivering up to 25 A continuous current. The PVIN device has programmable switching frequency of 300 kHz to 1.5 MHz. The control scheme delivers fast transient SW response and minimizes external components. Thanks to the internal current ramp information, no high ESR output Load PGND bulk or virtual ESR network is required for the loop stability. Constant on time This device also incorporates a power saving feature by PWM generator enabling diode emulation mode and frequency fold back as the load decreases. V Ramp generator SEN+ Comparator Differential In addition, a built in PLL allows in phase or 180° out of amplifier OTA phase synchronization under master / slave configuration. V REF SEN- C R P comp SiC45x has a full set of protection and monitoring features Ccomp with response that can be set with PMBus: AGND • Over current protection in pulse-by-pulse mode
Fig. 5 - VM-COT Block Diagram
• Output over voltage protection All components for RAMP signal generation and error • Output under voltage protection amplifier compensation required for the control loop are • Over temperature protection with hysteresis internal to the IC, see Fig. 5. In order for the device to cover • Dedicated enable pin for easy power sequencing a wide range of VOUT operation, the internal RAMP signal • Power good open drain output components are automatically selected depending on the V This device is available in MLP34-57 package to deliver high OUT voltage and switching frequency. The error amplifier internal compensation consists of a resistor in series with a power density and minimize PCB area. capacitor (RCOMP, CCOMP).
PWM Control Mechanism
Fig. 6 demonstrates the basic operational waveforms: SiC45x employs a voltage - mode COT control mechanism. During steady-state operation, feedback voltage is Basic operational waveforms compared with internal reference and the amplified error signal (VCOMP) is generated in the internal comp node. An internally generated ramp signal and V V COMP are fed into a RAMP comparator. Once VRAMP crosses VCOMP, a single shot on-time pulse is generated for a fixed time, programmed by the external Rfsw. During the on-time pulse, the high side MOSFET will be turned on. Once the on-time pulse expires, VCOMP the low side MOSFET will be turned on after a break-before-make period. The low side MOSFET will be on for duration of minimum off-time pulse until VRAMP crosses VCOMP. The cycle is then repeated. Fig. 5 illustrates the basic block diagram for VM-COT architecture. In this architecture the following is achieved: PWM Fixed on-time • The reference of a basic ripple control regulator is
Fig. 6 - VM-COT Operational Principle
replaced with a high again error amplifier loop
Light Load Condition
• This establishes two parallel voltage regulating feedback To improve efficiency at light-load condition, SiC45x paths, a fast and slow path provide a set of innovative implementations to eliminate LS • Fast path is the ripple injection which ensures rapid recirculating current and switching losses. The internal zero correction of the transient perturbation crossing detector monitors SW node voltage to determine • Slow path is the error amplifier loop which ensures the DC when inductor current starts to flow negatively. In power component of the output voltage follows the internal saving mode, as soon as inductor valley current crosses accurate reference voltage zero, the device deploys diode emulation mode by turning off low side MOSFET. If load further decreases, switching frequency is reduced proportional to load condition to save switching losses while keeping output ripple within tolerance. The switching frequency is set by the controller to S21-0213-Rev. B, 08-Mar-2021
7
Document Number: 77863 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000