Datasheet SiC450, SiC451, SiC453 (Vishay) - 8

SiC450, SiC451, SiC453
www.vishay.com Vishay Siliconix maintain regulation. In the standard power save mode, there pulses in a row, secondary level OC fault is recognized and is no minimum switching frequency. If ultrasonic mode is both HS and LS MOSFETs are turned off. The device selected via PMBus, the minimum switching frequency that continues restart attempt in a delay time until the OC fault the regulator will reduce to is > 20 kHz as the part avoids condition no longer exists. switching frequencies in the audible range. The consecutive switching pulse in a row, the delay time,
Power Stage
and other types of fault responses can be programmed via PMBus (see PMBus command section). The default number SiC45x integrates a high performance power stage with a is 128 for counting consecutive switching pulse in a row. 4 mΩ n-channel high side MOSFET and a 1.4 mΩ n-channel The default delay time is 20 ms. low side MOSFET. The MOSFETs are optimized to achieve up to 96 % efficiency. The OCP is enabled immediately after VDD passes UVLO level. The power input voltage (PVIN) can go up to 20 V and down as low as 4.5 V. The output voltage must always be less than the input voltage.
Sequencing of Input / Output Supplies
SiC45x has no sequencing requirements on any of its OCP input / output, PV threshold IN, PVCC, VIN, VDD and EN. VIN is internal supply voltage and is used to implement on time of COT I control. V load IN shall be directly connected to PVIN. I
EN
inductor The SiC45x has an EN pin to turn the part on and off. Driving this pin high enables the device, while grounding it turns it off. GH There are no sequencing requirements with respect to Skipped GH pulse input / output supplies.
Fig. 7 - Over-Current Protection Illustration Output Overcurrent Protection (OCP) Output Undervoltage Protection (UVP)
SiC45x has pulse-by-pulse overcurrent (OC) limit control. UVP is implemented by monitoring the output voltage. If the The inductor valley current is monitored during low-side (LS) output voltage drops below a threshold voltage FET turn-on period through RDS(on) sensing. After a VOUT_UV_FAULT_LIMIT (VUFL), the output-undervoltage (UV) pre-defined blanking time, the valley current is compared fault condition is recognized and both the HS and LS with an internal OCP threshold named MOSFETs are turned off. The device continues restart IOUT_OC_FAULT_LIMIT, which can be programmed via attempt in a delay time until the UV condition no longer PMBus. Once monitored valley current is larger than exists. IOUT_OC_FAULT_LIMIT, a pulse-by-pulse over-current The V limit is broken, high-side (HS) turn-on pulse is skipped and UFL and the delay time can be programmed via PMBus (see PMBus command section). The default value of V LS FET is kept on until the inductor valley current returns UFL is 20 % less than the target V below OCP limit as illustrated by Fig. 7. OUT. The default delay time is 20 ms. An equation is given in (1) to calculate The UVP is only active after the completion of soft-start IOUT_OC_FAULT_LIMIT from steady-state value of DC load sequence. current when OCP happens.
Output-Overvoltage Protection (OVP)
IOUT_OC_FAULT_LIMIT = OVP is implemented by monitoring the output voltage. If the output voltage is above a threshold voltage (PV – V ) × V I IN OUT OUT – ----------------------------- OUT_OCP (1) VOUT_OV_FAULT_LIMIT (VOFL), the output-overvoltage (OV) fault 2 × L × PV × f IN SW condition is recognized and both the HS and LS MOSFETs are turned off. The device restarts when the OV fault where: IOUT_OC_FAULT_LIMIT is the OCP threshold to be condition no longer exists. programmed via PMBus; IOUT_OCP is the steady-state value The UVFL can be programmed via PMBus (see PMBus of DC load current when pulse-by-pulse OC event happens; command section). The default value of VOFL is 15 % more PVIN is the input voltage for power stage; VOUT is the output than the target VOUT. voltage for power stage; L is inductance of power inductor; The OVP is enabled immediately after VDD passes UVLO and fSW is switching frequency for power stage. level. SiC45x also provides secondary level OCP protection. If the pulse-by-pulse overcurrent limit is persistently broken for more than a specific number of consecutive switching S21-0213-Rev. B, 08-Mar-2021
8
Document Number: 77863 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000