Datasheet STGAP2SICS (STMicroelectronics) - 9

STGAP2SICS Control inputs 6.3 Control inputs
The device is controlled through the IN+ and IN- logic inputs, in accordance with the truth table below.
Table 9. Inputs truth table (applicable when device is not in UVLO or "safe state") Input pins Output pins
IN+ IN- GON GOFF L L OFF ON H L ON OFF L H OFF ON H H OFF ON A deglitch filter allows input signals with duration shorter than tdeglitch to be ignored, thereby preventing noise spikes potentially present in the application from generating unwanted commutations.
6.4 Miller Clamp function
The Miller clamp function allows the control of the Miller current during the power stage switching in half-bridge configurations. When the external power transistor is in the OFF state, the driver operates to avoid the induced turn-on phenomenon that may occur when the other switch in the same leg is being turned on, due to the CGD capacitance. During the turn-off period the gate of the external switch is monitored through the CLAMP pin. The CLAMP switch is activated when gate voltage goes below the voltage threshold, VCLAMPth, thus creating a low impedance path between the switch gate and the GNDISO pin.
6.5 Watchdog
The isolated HV side has a watchdog function in order to identify when it is not able to communicate with LV side, for example because the VDD of the LV side is not supplied. In this case the output of the driver is forced in “safe state” until communication link is properly established again.
6.6 Thermal shutdown protection
The device provides a thermal shutdown protection. When junction temperature reaches the TSD temperature threshold, the device is forced in “safe state”. The device operation is restored as soon as the junction temperature is lower than TSD-Thys.
DS13402
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Rev 1 page 9/24
Document Outline Cover image Product status link / summary Features Application Description 1 Block diagram 2 Pin description and connection diagram 3 Electrical data 3.1 Absolute maximum ratings 3.2 Thermal data 3.3 Recommended operating conditions 4 Electrical characteristics 5 Isolation 6 Functional description 6.1 Gate driving power supply and UVLO 6.2 Power-up, power-down and “safe state” 6.3 Control inputs 6.4 Miller Clamp function 6.5 Watchdog 6.6 Thermal shutdown protection 6.7 Standby function 7 Typical application diagram 8 Layout 8.1 Layout guidelines and considerations 8.2 Layout example 9 Testing and characterization information 10 Package information 10.1 SO-8W package information 10.2 SO-8W suggested land pattern 11 Ordering information Revision history Contents List of tables List of figures