Datasheet HMC943APM5E (Analog Devices) - 14

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HMC943APM5E Data Sheet THEORY OF OPERATION
The HMC943APM5E is a GaAs, pHEMT, MMIC, >1.5 W power Device drain connections for al stages are available at the package amplifier consisting of four cascaded gain stages. A simplified leads. Gate voltage bias can be applied to either VG1 or VG2 schematic is shown in Figure 48. The input signal is evenly divided because the bias is internally connected to the gates of devices and amplified through four gain stages. These amplified signals for all stages. are then recombined at the output. Both inputs and outputs are internal y matched to 50 Ω for ease of use.
VG1 VD1 VD3 VD5 VD7 RFIN RFOUT VD2 VD4 VD6 VD8
045
VG2
16864- Figure 48. Simplified Schematic Diagram of Amplifier Stages Rev. B | Page 14 of 18 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION POWER DETECTION EVALUATION BOARD EVALUATION BOARD SCHEMATIC OUTLINE DIMENSIONS ORDERING GUIDE