Datasheet ISL9122A (Renesas) - 7
| 制造商 | Renesas |
| 描述 | Ultra-Low IQ Buck-Boost Regulator with Bypass |
| 页数 / 页 | 21 / 7 |
| 文件格式/大小 | PDF / 902 Kb |
| 文件语言 | 英语 |
该数据表的模型线
文件文字版本
ISL9122A 2. Specifications VIN = VEN = 3.6V, VOUT = 3.3V, I2C pull-up voltage = VIN, L1 = 1µH, C1 = 10µF, effective C2 = 6µF, TA = +25°C.
Boldface limits apply across the recommended operating temperature range (-40°C to +85°C) and input voltage range (1.8V to 5.5V), unless specified otherwise. (Continued) Min Max Parameter Symbol Test Conditions (Note 4) Typ (Note 4) Unit Switching Frequency
Switching Frequency fSW VIN = 3.6V, VOUT = 1.8V, IOUT = 1mA, Forced 2.5 MHz PWM
Hiccup Mode
Hiccup Time tFLT_WAIT Time from shutdown to restart 100 ms
Thermal Protection
Thermal Shutdown Threshold TSD Rising Temperature 130 °C Thermal Shutdown Hysteresis TSD_HYS 25 °C
Logic Levels
Input Leakage ILEAK EN pin 9 300 nA SCL pin 8 300 nA SDA pin 8 300 nA EN Input HIGH Voltage ENIH VIN = 3.6V
1.6
V EN Input LOW Voltage ENIL
0.36
V SCL/SDA Input HIGH Voltage SCL/SDAIH
1.45
V SCL/SDA Input LOW Voltage SCL/SDAIL
0.36
V
Notes:
4. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 5. Quiescent current measurements are taken when the device is not switching.
FN8947 Rev.1.00 Page 7 of 20 Sep.14.20 Document Outline Features Applications Related Literature Contents 1. Overview 1.1 Block Diagram 1.2 Ordering Information 1.3 Pin Configurations 1.4 Pin Descriptions 2. Specifications 2.1 Absolute Maximum Ratings 2.2 Thermal Information 2.3 Recommended Operation Conditions 2.4 Analog Specifications 2.5 I2C Interface Timing Specifications 3. Typical Performance Curves 4. Functional Description 4.1 Enable Input 4.2 Soft Discharge 4.3 Start-Up 4.4 Overcurrent/Short-Circuit Protection 4.5 Thermal Shutdown 4.6 Buck-Boost Conversion Topology 4.7 PWM Operation 4.8 PFM Operation 4.9 Operation With VIN Close to VOUT 4.10 Forced Operating Modes 4.11 I2C Serial Interface 4.12 Protocol Conventions 4.13 Write Operation 4.14 Read Operation 4.15 Register Descriptions 4.15.1 RO_REG1 4.15.2 INTFLG_REG 4.15.3 VSET 4.15.4 CONV_CFG 4.15.5 INTFLG_MASK 5. Revision History 6. Package Outline Drawings
Boldface limits apply across the recommended operating temperature range (-40°C to +85°C) and input voltage range (1.8V to 5.5V), unless specified otherwise. (Continued) Min Max Parameter Symbol Test Conditions (Note 4) Typ (Note 4) Unit Switching Frequency
Switching Frequency fSW VIN = 3.6V, VOUT = 1.8V, IOUT = 1mA, Forced 2.5 MHz PWM
Hiccup Mode
Hiccup Time tFLT_WAIT Time from shutdown to restart 100 ms
Thermal Protection
Thermal Shutdown Threshold TSD Rising Temperature 130 °C Thermal Shutdown Hysteresis TSD_HYS 25 °C
Logic Levels
Input Leakage ILEAK EN pin 9 300 nA SCL pin 8 300 nA SDA pin 8 300 nA EN Input HIGH Voltage ENIH VIN = 3.6V
1.6
V EN Input LOW Voltage ENIL
0.36
V SCL/SDA Input HIGH Voltage SCL/SDAIH
1.45
V SCL/SDA Input LOW Voltage SCL/SDAIL
0.36
V
Notes:
4. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 5. Quiescent current measurements are taken when the device is not switching.
FN8947 Rev.1.00 Page 7 of 20 Sep.14.20 Document Outline Features Applications Related Literature Contents 1. Overview 1.1 Block Diagram 1.2 Ordering Information 1.3 Pin Configurations 1.4 Pin Descriptions 2. Specifications 2.1 Absolute Maximum Ratings 2.2 Thermal Information 2.3 Recommended Operation Conditions 2.4 Analog Specifications 2.5 I2C Interface Timing Specifications 3. Typical Performance Curves 4. Functional Description 4.1 Enable Input 4.2 Soft Discharge 4.3 Start-Up 4.4 Overcurrent/Short-Circuit Protection 4.5 Thermal Shutdown 4.6 Buck-Boost Conversion Topology 4.7 PWM Operation 4.8 PFM Operation 4.9 Operation With VIN Close to VOUT 4.10 Forced Operating Modes 4.11 I2C Serial Interface 4.12 Protocol Conventions 4.13 Write Operation 4.14 Read Operation 4.15 Register Descriptions 4.15.1 RO_REG1 4.15.2 INTFLG_REG 4.15.3 VSET 4.15.4 CONV_CFG 4.15.5 INTFLG_MASK 5. Revision History 6. Package Outline Drawings