Datasheet ISL9122A (Renesas) - 9

制造商Renesas
描述Ultra-Low IQ Buck-Boost Regulator with Bypass
页数 / 页21 / 9 — Typical Performance Curves. 100. LOAD = 10mA. LOAD = 100mA LOAD = 500mA. …
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Typical Performance Curves. 100. LOAD = 10mA. LOAD = 100mA LOAD = 500mA. VOUT (3.3V_OFFSET, 20mV/Div). VIN (2V/Div). y (%)

Typical Performance Curves 100 LOAD = 10mA LOAD = 100mA LOAD = 500mA VOUT (3.3V_OFFSET, 20mV/Div) VIN (2V/Div) y (%)

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ISL9122A 3. Typical Performance Curves
3. Typical Performance Curves
VIN = VEN = 3.6V, VOUT = 3.3V, I2C pull-up voltage = VIN, L1 = 1µH, C1 = 10µF, C2 = 10µF, TA = +25°C, unless otherwise stated.
100 LOAD = 10mA 98 LOAD = 100mA LOAD = 500mA VOUT (3.3V_OFFSET, 20mV/Div) 96 VIN (2V/Div) 94 y (%) 92 fficienc E 90 LX2 (2V/Div) 88 LX1 (2V/Div) 86 1.8 2.8 3.8 4.8 5.8 VIN (V) 400ns/Div Figure 4. Efficiency vs Input Voltage: VOUT = 3.3V, Figure 5. Steady-State Operation in PFM: VIN = 2.0V, 1.0μH Coilcraft XEL4020, TA = +25°C VOUT = 3.3V, No Load VIN (2V/Div) VIN (2V/Div) VOUT (3.3V_OFFSET, 20mV/Div) VOUT (3.3V_OFFSET, 20mV/Div) LX2 (2V/Div) LX2 (2V/Div) LX1 (2V/Div) LX1 (2V/Div) 400ns/Div 400ns/Div Figure 6. Steady-State Operation in PFM: VIN = 3.6V, Figure 7. Steady-State Operation in PFM: VIN = 5.0V, VOUT = 3.3V, No Load VOUT = 3.3V, No Load
FN8947 Rev.1.00 Page 9 of 20 Sep.14.20 Document Outline Features Applications Related Literature Contents 1. Overview 1.1 Block Diagram 1.2 Ordering Information 1.3 Pin Configurations 1.4 Pin Descriptions 2. Specifications 2.1 Absolute Maximum Ratings 2.2 Thermal Information 2.3 Recommended Operation Conditions 2.4 Analog Specifications 2.5 I2C Interface Timing Specifications 3. Typical Performance Curves 4. Functional Description 4.1 Enable Input 4.2 Soft Discharge 4.3 Start-Up 4.4 Overcurrent/Short-Circuit Protection 4.5 Thermal Shutdown 4.6 Buck-Boost Conversion Topology 4.7 PWM Operation 4.8 PFM Operation 4.9 Operation With VIN Close to VOUT 4.10 Forced Operating Modes 4.11 I2C Serial Interface 4.12 Protocol Conventions 4.13 Write Operation 4.14 Read Operation 4.15 Register Descriptions 4.15.1 RO_REG1 4.15.2 INTFLG_REG 4.15.3 VSET 4.15.4 CONV_CFG 4.15.5 INTFLG_MASK 5. Revision History 6. Package Outline Drawings