Preliminary Datasheet ADSP-21562, ADSP-21563, ADSP-21565 (Analog Devices)

SHARC+ Single Core High Performance DSP (Up to 1 GHz) Preliminary Technical Data ADSP-21562/21563/21565 SYSTEM FEATURES MEMORY Enhanced SHARC+ high performance floating-point core Large on-chip Level 2 (L2) SRAM with ECC protection, up to Up to 1 GHz 8 Mb (1 MB) Up to 5 Mb (640 kB) Level 1 (L1) SRAM memory with parity One Level 3 (L3) interface optimized for low system power, (optional ability to configure as cache) providing 16-bit interface to DDR3/ DDR3L SDRAM devices 32-bit, 40-bit, and 64-bit floating-point support ADDITIONAL FEATURES 32-bit fixed point Security and Protection Byte, short-word, word, long-word addressed Crypto hardware accelerators Powerful DMA system Fast secure boot with IP protection On-chip memory protection Enhanced FIR and IIR accelerators running up to 1 GHz Integrated safety features 17 mm × 17 mm 400 CSP_BGA (0.8 mm pitch), RoHS APPLICATIONS compliant Automotive: audio amplifier, head unit, ANC/RNC, rear seat 120-lead LQFP_EP (0.4 mm pitch), RoHS compliant entertainment, digital cockpit, ADAS Low system power across automotive temperature range Consumer: speakers, sound bars, AVRs, conferencing sys- tems, mixing consoles, microphone arrays, headphones SYSTEM CONTROL SHARC+ CORE SECURITY AND PROTECTION UP TO SYSTEM PROTECTION UNIT (SPU) 1 GHz FLOATING-POINT
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SYSTEM MEMORY DSP PROTECTION UNIT (SMPU) PERIPHERALS FAULT MANAGEMENT (FMU) SIGNAL ROUTING UNIT (SRU) 2×2 PRECISION CLOCK DUAL CRC (WITH MemDMA) L1 SRAM (PARITY) GENERATORS Up to 5 Mb (640 kB) WATCHDOGS 2x DAI 2×4 ASRC FULL SPORT 2x PIN SRAM/CACHE OTP MEMORY PAIRS 2×4 BUFFER 24–28 2×1 S/PDIF Rx/Tx PROGRAM FLOW SYSTEM EVENT CONTROLLER 6× I2C (SEC) SYSTEM CROSSBAR AND DMA SUBSYSTEM 1× SPI + 2× QUAD SPI + TRIGGER ROUTING UNIT (TRU) 1× OCTAL SPI G 3× UARTs P CLOCK, RESET, AND POWER I 22–40 2× LINK PORTS CLOCK GENERATION UNIT (CGU) O L3 MEMORY SYSTEM SYSTEM 10× TIMERS + 1× COUNTER CLOCK DISTRIBUTION UNIT (CDU) INTERFACES L2 MEMORY ACCELERATION MLB 3-PIN RESET CONTROL UNIT (RCU) DSP FUNCTIONS DDR3/DDR3L SRAM (FIR, IIR) DYNAMIC POWER MANAGEMENT (ECC) BGA ONLY (DPM) UP TO 8 Mb (1 MB) ENCRYPTION/ DECRYPTION DEBUG UNIT 16 ARM® CoreSight TM DATA DEBUG AND TRACE SYSTEM WATCHPOINT UNIT (SWU)
Figure 1. Processor Block Diagram SHARC, SHARC+, and the SHARC logo are registered trademarks of Analog Devices, Inc.
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Document Outline System Features Memory Additional Features Applications Table of Contents Revision History General Description SHARC Processor L1 Memory L1 Master and Slave Ports L1 On-Chip Memory Bandwidth Instruction and Data Cache System Event Controller (SEC) Input Core Memory-Mapped Registers (CMMR) SHARC+ Core Architecture Single-Instruction, Multiple Data (SIMD) Computational Engine Independent Parallel Computation Units Core Timer Data Register File Context Switch Universal Registers Data Address Generators (DAG) With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Architecture (ISA) Variable Instruction Set Architecture (VISA) Single-Cycle Fetch of Instructional Four Operands Core Event Controller (CEC) Instruction Conflict Cache Branch Target Buffer (BTB)/Branch Predictor (BP) Addressing Spaces Additional Features System Infrastructure System L2 Memory One Time Programmable Memory (OTP) I/O Memory Space System Memory Map System Crossbars (SCBs) Direct Memory Access (DMA) Memory Direct Memory Access (MDMA) Extended Memory DMA Cyclic Redundant Code (CRC) Protection Event Handling System Event Controller (SEC) Trigger Routing Unit (TRU) Security Features Cryptographic Hardware Accelerators System Protection Unit (SPU) System Memory Protection Unit (SMPU) Security Features Disclaimer Safety Features Multiparity Bit Protected SHARC+ Core L1 Memories Error Correcting Codes (ECC) Protected L2 Memories Parity-Protected Peripheral Memories Cyclic Redundant Code (CRC) Protected Memories Signal Watchdogs System Event Controller (SEC) Memory Error Controller (MEC) Processor Peripherals Dynamic Memory Controller (DMC) Digital Audio Interface (DAI) Serial Port (SPORT) Asynchronous Sample Rate Converter (ASRC) S/PDIF-Compatible Digital Audio Receiver/Transmitter Precision Clock Generators (PCG) Universal Asynchronous Receiver/Transmitter (UART) Ports Serial Peripheral Interface (SPI) Ports Octal Serial Peripheral Interface (OSPI) Port Link Port (LP) Timers General-Purpose (GP) Timers (TIMER) Watchdog Timer (WDT) General-Purpose Counters (CNT) Media Local Bus (MediaLB) 2-Wire Controller Interface (TWI) General-Purpose I/O (GPIO) Pin Interrupts System Acceleration Finite Impulse Response (FIR) Accelerator Infinite Impulse Response (IIR) Accelerator System Design Clock Management Reset Control Unit (RCU) Clock Generation Unit (CGU) System Crystal Oscillator Clock Distribution Unit (CDU) Clock Out/External Clock Booting Power Supplies Power Management Power-Up and Power-Down Sequencing Target Board JTAG Emulator Connector System Debug System Watchpoint Unit (SWU) Debug Access Port (DAP) Development Tools Integrated Development Environments (IDEs) EZ-KIT Evaluation Board EZ-KIT Evaluation Kits Software Add Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-2156x Detailed Signal Descriptions 400-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 400-Ball CSP_BGA Package 120-Lead LQFP Signal Descriptions GPIO Multiplexing for 120-Lead LQFP ADSP-2156x Designer Quick Reference Preliminary Specifications Preliminary Operating Conditions Preliminary Clock Related Operating Conditions Preliminary Electrical Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications Power-Up Reset Timing Clock and Reset Timing Link Ports (LPs) Serial Ports (SPORTs) Asynchronous Sample Rate Converter (ASRC)—Serial Input Port Asynchronous Sample Rate Converter (ASRC)—Serial Output Port SPI Port—Master Timing SPI0, SPI1, and SPI2 SPI Port—Slave Timing SPI0, SPI1, and SPI2 SPI Port—SPIx_RDY Slave Timing SPI Port—Open Drain Mode (ODM) Timing SPI Port—SPIx_RDY Master Timing OSPI Port—Master Timing OSPI0 Precision Clock Generator (PCG) (Direct Pin Routing) General-Purpose IO Port Timing General-Purpose I/O Timer Cycle Timing DAIx Pin to DAIx Pin Direct Routing (DAI0 Block and DAI1 Block) Up/Down Counter/Rotary Encoder Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Sony/Philips Digital Interface (S/PDIF) Transmitter S/PDIF Transmitter Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode MediaLB (MLB) Program Trace Macrocell (PTM) Timing Debug Interface (JTAG Emulation Port) Timing ADSP-2156x 400-Ball BGA Ball Assignments ADSP-2156x 400-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-2156x 400-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 400-Ball CSP_BGA ADSP-2156x 120-Lead LQFP Lead Assignments ADSP-2156x 120-Lead LQFP Lead Assignments (Numerical by Lead Number) ADSP-2156x 120-Lead LQFP Lead Assignments (Alphabetical by Pin Name) Configuration of the 120-Lead LQFP Lead Configuration Outline Dimensions Surface-Mount Design Planned Automotive Production Products Planned Production Products Pre Release Products