Datasheet ADN8833 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | Ultracompact, 1 A Thermoelectric Cooler (TEC) Driver for Digital Control Systems |
| 页数 / 页 | 23 / 10 — ADN8833. Data Sheet. TEC CURRENT. LDO (TEC+). LDO (TEC–). PWM (TEC+). PWM … |
| 修订版 | B |
| 文件格式/大小 | PDF / 1.6 Mb |
| 文件语言 | 英语 |
ADN8833. Data Sheet. TEC CURRENT. LDO (TEC+). LDO (TEC–). PWM (TEC+). PWM (TEC–). CH1 1V. CH2 1V. CH3 2V. M20.0ms. A CH3 800mV. CH1 20mV
该数据表的模型线
文件文字版本
ADN8833 Data Sheet T EN SW 3 3 TEC CURRENT 4 LDO (TEC+) LDO (TEC–) 1 PWM (TEC+) PWM (TEC–) 2 1
121 102
CH1 1V CH2 1V CH3 2V M20.0ms A CH3 800mV CH1 20mV BW CH2 20mV B M400ns A CH3 1.00V W CH4 500mA Ω T 40ms CH3 2.0V B T 0.0s
12909-
W
12909- Figure 16. Typical Enable Waveforms in Cooling Mode, VIN = 3.3 V, Figure 18. Typical Switch and Voltage Ripple Waveforms in Cooling Mode, Load = 2 Ω, TEC Current = 1 A VIN = 3.3 V, Load = 2 Ω, TEC Current = 1 A
T EN SW 3 3 TEC CURRENT 4 LDO (TEC+) 1 PWM (TEC–) PWM (TEC–) 2 LDO (TEC+) 2
122 103
CH1 1V CH2 1V CH3 2V M20.0ms A CH3 800mV CH1 20mV BW CH2 20mV B M400ns A CH3 1.00V W CH4 500mA Ω T 40ms CH3 2.0V B T 0.0s
12909-
W
12909- Figure 17. Enable Waveforms in Heating Mode, VIN = 3.3 V, Figure 19. Typical Switch and Voltage Ripple Waveforms in Heating Mode, Load = 2 Ω, TEC Current = 1 A VIN = 3.3 V, Load = 2 Ω, TEC Current = 1 A Rev. B | Page 10 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS DETAILED FUNCTIONAL BLOCK DIAGRAM THEORY OF OPERATION DIGITAL PID CONTROL POWERING THE DRIVER ENABLE AND SHUTDOWN OSCILLATOR CLOCK FREQUENCY External Clock Operation Connecting Multiple ADN8833 Devices SOFT START ON POWER-UP TEC VOLTAGE/CURRENT MONITOR Voltage Monitor Current Monitor MAXIMUM TEC VOLTAGE LIMIT Using a Resistor Divider to Set the TEC Voltage Limit MAXIMUM TEC CURRENT LIMIT Using a Resistor Divider to Set the TEC Current Limit APPLICATIONS INFORMATION TYPICAL APPLICATION WITH DIGITAL PID USING A DAC THERMISTOR SETUP MOSFET DRIVER AMPLIFIERS PWM OUTPUT FILTER REQUIREMENTS Inductor Selection Capacitor Selection INPUT CAPACITOR SELECTION POWER DISSIPATION PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Linear Regulator Power Dissipation PCB LAYOUT GUIDELINES BLOCK DIAGRAMS AND SIGNAL FLOW GUIDELINES FOR REDUCING NOISE AND MINIMIZING POWER LOSS General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines EXAMPLE PCB LAYOUT USING TWO LAYERS OUTLINE DIMENSIONS ORDERING GUIDE
121 102
CH1 1V CH2 1V CH3 2V M20.0ms A CH3 800mV CH1 20mV BW CH2 20mV B M400ns A CH3 1.00V W CH4 500mA Ω T 40ms CH3 2.0V B T 0.0s
12909-
W
12909- Figure 16. Typical Enable Waveforms in Cooling Mode, VIN = 3.3 V, Figure 18. Typical Switch and Voltage Ripple Waveforms in Cooling Mode, Load = 2 Ω, TEC Current = 1 A VIN = 3.3 V, Load = 2 Ω, TEC Current = 1 A
T EN SW 3 3 TEC CURRENT 4 LDO (TEC+) 1 PWM (TEC–) PWM (TEC–) 2 LDO (TEC+) 2
122 103
CH1 1V CH2 1V CH3 2V M20.0ms A CH3 800mV CH1 20mV BW CH2 20mV B M400ns A CH3 1.00V W CH4 500mA Ω T 40ms CH3 2.0V B T 0.0s
12909-
W
12909- Figure 17. Enable Waveforms in Heating Mode, VIN = 3.3 V, Figure 19. Typical Switch and Voltage Ripple Waveforms in Heating Mode, Load = 2 Ω, TEC Current = 1 A VIN = 3.3 V, Load = 2 Ω, TEC Current = 1 A Rev. B | Page 10 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS DETAILED FUNCTIONAL BLOCK DIAGRAM THEORY OF OPERATION DIGITAL PID CONTROL POWERING THE DRIVER ENABLE AND SHUTDOWN OSCILLATOR CLOCK FREQUENCY External Clock Operation Connecting Multiple ADN8833 Devices SOFT START ON POWER-UP TEC VOLTAGE/CURRENT MONITOR Voltage Monitor Current Monitor MAXIMUM TEC VOLTAGE LIMIT Using a Resistor Divider to Set the TEC Voltage Limit MAXIMUM TEC CURRENT LIMIT Using a Resistor Divider to Set the TEC Current Limit APPLICATIONS INFORMATION TYPICAL APPLICATION WITH DIGITAL PID USING A DAC THERMISTOR SETUP MOSFET DRIVER AMPLIFIERS PWM OUTPUT FILTER REQUIREMENTS Inductor Selection Capacitor Selection INPUT CAPACITOR SELECTION POWER DISSIPATION PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Linear Regulator Power Dissipation PCB LAYOUT GUIDELINES BLOCK DIAGRAMS AND SIGNAL FLOW GUIDELINES FOR REDUCING NOISE AND MINIMIZING POWER LOSS General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines EXAMPLE PCB LAYOUT USING TWO LAYERS OUTLINE DIMENSIONS ORDERING GUIDE