Datasheet ADN8833 (Analog Devices) - 2
| 制造商 | Analog Devices |
| 描述 | Ultracompact, 1 A Thermoelectric Cooler (TEC) Driver for Digital Control Systems |
| 页数 / 页 | 23 / 2 — ADN8833. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 8/2018—Rev. A … |
| 修订版 | B |
| 文件格式/大小 | PDF / 1.6 Mb |
| 文件语言 | 英语 |
ADN8833. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 8/2018—Rev. A to Rev. B. 8/2015—Rev. 0 to Rev. A
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ADN8833 Data Sheet TABLE OF CONTENTS
Features .. 1 TEC Voltage/Current Monitor ... 15 Applications ... 1 Maximum TEC Voltage Limit .. 15 Functional Block Diagram .. 1 Maximum TEC Current Limit ... 15 General Description ... 1 Applications Information .. 16 Revision History ... 2 Typical Application with Digital PID Using a DAC .. 16 Specifications ... 3 Thermistor Setup .. 16 Absolute Maximum Ratings .. 6 MOSFET Driver Amplifiers .. 16 Thermal Resistance .. 6 PWM Output Filter Requirements .. 17 ESD Caution .. 6 Input Capacitor Selection .. 18 Pin Configurations and Function Descriptions ... 7 Power Dissipation... 18 Typical Performance Characteristics ... 8 PCB Layout Guidelines .. 20 Detailed Functional Block Diagram .. 12 Block Diagrams and Signal Flow ... 20 Theory of Operation .. 13 Guidelines for Reducing Noise and Minimizing Power Loss .. 20 Digital PID Control .. 13 Example PCB Layout Using Two Layers ... 21 Powering the Driver ... 13 Outline Dimensions ... 23 Enable and Shutdown .. 14 Ordering Guide .. 23 Oscillator Clock Frequency ... 14 Soft Start on Power-Up .. 14
REVISION HISTORY 8/2018—Rev. A to Rev. B
Added Patent Information .. 1
8/2015—Rev. 0 to Rev. A
Added 24-Lead LFCSP ... Universal Changes to Features Section and Table 1 .. 1 Changes to Table 2 .. 3 Changes to Table 3 .. 6 Added Figure 3; Renumbered Sequentially ... 7 Changes to Figure 11 .. 9 Changes to Figure 18 and Figure 19 ... 10 Changes to Figure 23 .. 12 Changes to Powering the Driver Section and Figure 24 Caption ... 13 Change to Soft Start on Power-Up Section ... 14 Changes to Table 7 .. 17 Added Table 8; Renumbered Sequentially .. 18 Updated Outline Dimensions ... 23 Changes to Ordering Guide ... 23
4/2015—Revision 0: Initial Version
Rev. B | Page 2 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS DETAILED FUNCTIONAL BLOCK DIAGRAM THEORY OF OPERATION DIGITAL PID CONTROL POWERING THE DRIVER ENABLE AND SHUTDOWN OSCILLATOR CLOCK FREQUENCY External Clock Operation Connecting Multiple ADN8833 Devices SOFT START ON POWER-UP TEC VOLTAGE/CURRENT MONITOR Voltage Monitor Current Monitor MAXIMUM TEC VOLTAGE LIMIT Using a Resistor Divider to Set the TEC Voltage Limit MAXIMUM TEC CURRENT LIMIT Using a Resistor Divider to Set the TEC Current Limit APPLICATIONS INFORMATION TYPICAL APPLICATION WITH DIGITAL PID USING A DAC THERMISTOR SETUP MOSFET DRIVER AMPLIFIERS PWM OUTPUT FILTER REQUIREMENTS Inductor Selection Capacitor Selection INPUT CAPACITOR SELECTION POWER DISSIPATION PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Linear Regulator Power Dissipation PCB LAYOUT GUIDELINES BLOCK DIAGRAMS AND SIGNAL FLOW GUIDELINES FOR REDUCING NOISE AND MINIMIZING POWER LOSS General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines EXAMPLE PCB LAYOUT USING TWO LAYERS OUTLINE DIMENSIONS ORDERING GUIDE
ADN8833 Data Sheet TABLE OF CONTENTS
Features .. 1 TEC Voltage/Current Monitor ... 15 Applications ... 1 Maximum TEC Voltage Limit .. 15 Functional Block Diagram .. 1 Maximum TEC Current Limit ... 15 General Description ... 1 Applications Information .. 16 Revision History ... 2 Typical Application with Digital PID Using a DAC .. 16 Specifications ... 3 Thermistor Setup .. 16 Absolute Maximum Ratings .. 6 MOSFET Driver Amplifiers .. 16 Thermal Resistance .. 6 PWM Output Filter Requirements .. 17 ESD Caution .. 6 Input Capacitor Selection .. 18 Pin Configurations and Function Descriptions ... 7 Power Dissipation... 18 Typical Performance Characteristics ... 8 PCB Layout Guidelines .. 20 Detailed Functional Block Diagram .. 12 Block Diagrams and Signal Flow ... 20 Theory of Operation .. 13 Guidelines for Reducing Noise and Minimizing Power Loss .. 20 Digital PID Control .. 13 Example PCB Layout Using Two Layers ... 21 Powering the Driver ... 13 Outline Dimensions ... 23 Enable and Shutdown .. 14 Ordering Guide .. 23 Oscillator Clock Frequency ... 14 Soft Start on Power-Up .. 14
REVISION HISTORY 8/2018—Rev. A to Rev. B
Added Patent Information .. 1
8/2015—Rev. 0 to Rev. A
Added 24-Lead LFCSP ... Universal Changes to Features Section and Table 1 .. 1 Changes to Table 2 .. 3 Changes to Table 3 .. 6 Added Figure 3; Renumbered Sequentially ... 7 Changes to Figure 11 .. 9 Changes to Figure 18 and Figure 19 ... 10 Changes to Figure 23 .. 12 Changes to Powering the Driver Section and Figure 24 Caption ... 13 Change to Soft Start on Power-Up Section ... 14 Changes to Table 7 .. 17 Added Table 8; Renumbered Sequentially .. 18 Updated Outline Dimensions ... 23 Changes to Ordering Guide ... 23
4/2015—Revision 0: Initial Version
Rev. B | Page 2 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS DETAILED FUNCTIONAL BLOCK DIAGRAM THEORY OF OPERATION DIGITAL PID CONTROL POWERING THE DRIVER ENABLE AND SHUTDOWN OSCILLATOR CLOCK FREQUENCY External Clock Operation Connecting Multiple ADN8833 Devices SOFT START ON POWER-UP TEC VOLTAGE/CURRENT MONITOR Voltage Monitor Current Monitor MAXIMUM TEC VOLTAGE LIMIT Using a Resistor Divider to Set the TEC Voltage Limit MAXIMUM TEC CURRENT LIMIT Using a Resistor Divider to Set the TEC Current Limit APPLICATIONS INFORMATION TYPICAL APPLICATION WITH DIGITAL PID USING A DAC THERMISTOR SETUP MOSFET DRIVER AMPLIFIERS PWM OUTPUT FILTER REQUIREMENTS Inductor Selection Capacitor Selection INPUT CAPACITOR SELECTION POWER DISSIPATION PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Linear Regulator Power Dissipation PCB LAYOUT GUIDELINES BLOCK DIAGRAMS AND SIGNAL FLOW GUIDELINES FOR REDUCING NOISE AND MINIMIZING POWER LOSS General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines EXAMPLE PCB LAYOUT USING TWO LAYERS OUTLINE DIMENSIONS ORDERING GUIDE