Datasheet ADN8833 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | Ultracompact, 1 A Thermoelectric Cooler (TEC) Driver for Digital Control Systems |
| 页数 / 页 | 23 / 6 — ADN8833. Data Sheet. ABSOLUTE MAXIMUM RATINGS. THERMAL RESISTANCE. Table … |
| 修订版 | B |
| 文件格式/大小 | PDF / 1.6 Mb |
| 文件语言 | 英语 |
ADN8833. Data Sheet. ABSOLUTE MAXIMUM RATINGS. THERMAL RESISTANCE. Table 3. Parameter. Rating. Table 4. Package Type. θJA. θJC. Unit
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文件文字版本
ADN8833 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter Rating
θJA is specified for the worst-case conditions, that is, a device PVIN to PGNDL (WLCSP) −0.3 V to +5.75 V soldered in a circuit board for surface-mount packages, and is PVIN to PGNDS (WLCSP) −0.3 V to +5.75 V based on a 4-layer standard JEDEC board. PVINL to PGNDL (LFCSP) −0.3 V to +5.75 V
Table 4.
PVINS to PGNDS (LFCSP) −0.3 V to +5.75 V
Package Type θJA θJC Unit
LDR to PGNDL (WLCSP) −0.3 V to VPVIN 25-Ball WLCSP 48 0.6 °C/W LDR to PGNDL (LFCSP) −0.3 V to VPVINL 24-Lead LFCSP 37 1.65 °C/W SW to PGNDS −0.3 V to +5.75 V SFB to AGND −0.3 V to V VDD AGND to PGNDL −0.3 V to +0.3 V
ESD CAUTION
AGND to PGNDS −0.3 V to +0.3 V VLIM/SD to AGND −0.3 V to VVDD ILIM to AGND −0.3 V to VVDD VREF to AGND −0.3 V to +3 V VDD to AGND −0.3 V to +5.75 V EN/SY to AGND −0.3 V to VVDD ITEC to AGND −0.3 V to +5.75 V VTEC to AGND −0.3 V to +5.75 V Maximum Current VREF to AGND 20 mA ITEC to AGND 50 mA VTEC to AGND 50 mA Junction Temperature 125°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 10 sec) 260°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 6 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS DETAILED FUNCTIONAL BLOCK DIAGRAM THEORY OF OPERATION DIGITAL PID CONTROL POWERING THE DRIVER ENABLE AND SHUTDOWN OSCILLATOR CLOCK FREQUENCY External Clock Operation Connecting Multiple ADN8833 Devices SOFT START ON POWER-UP TEC VOLTAGE/CURRENT MONITOR Voltage Monitor Current Monitor MAXIMUM TEC VOLTAGE LIMIT Using a Resistor Divider to Set the TEC Voltage Limit MAXIMUM TEC CURRENT LIMIT Using a Resistor Divider to Set the TEC Current Limit APPLICATIONS INFORMATION TYPICAL APPLICATION WITH DIGITAL PID USING A DAC THERMISTOR SETUP MOSFET DRIVER AMPLIFIERS PWM OUTPUT FILTER REQUIREMENTS Inductor Selection Capacitor Selection INPUT CAPACITOR SELECTION POWER DISSIPATION PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Linear Regulator Power Dissipation PCB LAYOUT GUIDELINES BLOCK DIAGRAMS AND SIGNAL FLOW GUIDELINES FOR REDUCING NOISE AND MINIMIZING POWER LOSS General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines EXAMPLE PCB LAYOUT USING TWO LAYERS OUTLINE DIMENSIONS ORDERING GUIDE
θJA is specified for the worst-case conditions, that is, a device PVIN to PGNDL (WLCSP) −0.3 V to +5.75 V soldered in a circuit board for surface-mount packages, and is PVIN to PGNDS (WLCSP) −0.3 V to +5.75 V based on a 4-layer standard JEDEC board. PVINL to PGNDL (LFCSP) −0.3 V to +5.75 V
Table 4.
PVINS to PGNDS (LFCSP) −0.3 V to +5.75 V
Package Type θJA θJC Unit
LDR to PGNDL (WLCSP) −0.3 V to VPVIN 25-Ball WLCSP 48 0.6 °C/W LDR to PGNDL (LFCSP) −0.3 V to VPVINL 24-Lead LFCSP 37 1.65 °C/W SW to PGNDS −0.3 V to +5.75 V SFB to AGND −0.3 V to V VDD AGND to PGNDL −0.3 V to +0.3 V
ESD CAUTION
AGND to PGNDS −0.3 V to +0.3 V VLIM/SD to AGND −0.3 V to VVDD ILIM to AGND −0.3 V to VVDD VREF to AGND −0.3 V to +3 V VDD to AGND −0.3 V to +5.75 V EN/SY to AGND −0.3 V to VVDD ITEC to AGND −0.3 V to +5.75 V VTEC to AGND −0.3 V to +5.75 V Maximum Current VREF to AGND 20 mA ITEC to AGND 50 mA VTEC to AGND 50 mA Junction Temperature 125°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 10 sec) 260°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 6 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS DETAILED FUNCTIONAL BLOCK DIAGRAM THEORY OF OPERATION DIGITAL PID CONTROL POWERING THE DRIVER ENABLE AND SHUTDOWN OSCILLATOR CLOCK FREQUENCY External Clock Operation Connecting Multiple ADN8833 Devices SOFT START ON POWER-UP TEC VOLTAGE/CURRENT MONITOR Voltage Monitor Current Monitor MAXIMUM TEC VOLTAGE LIMIT Using a Resistor Divider to Set the TEC Voltage Limit MAXIMUM TEC CURRENT LIMIT Using a Resistor Divider to Set the TEC Current Limit APPLICATIONS INFORMATION TYPICAL APPLICATION WITH DIGITAL PID USING A DAC THERMISTOR SETUP MOSFET DRIVER AMPLIFIERS PWM OUTPUT FILTER REQUIREMENTS Inductor Selection Capacitor Selection INPUT CAPACITOR SELECTION POWER DISSIPATION PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Linear Regulator Power Dissipation PCB LAYOUT GUIDELINES BLOCK DIAGRAMS AND SIGNAL FLOW GUIDELINES FOR REDUCING NOISE AND MINIMIZING POWER LOSS General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines EXAMPLE PCB LAYOUT USING TWO LAYERS OUTLINE DIMENSIONS ORDERING GUIDE