Datasheet ADuCM3027, ADuCM3029 (Analog Devices) - 5

Data Sheet ADuCM3027/ ADuCM3029 POWER SUPPLY CURRENT SPECIFICATIONS Active Mode Table 4. Parameter Min Typ1 Max2 Unit Test Conditions/Comments
ACTIVE MODE3 Current consumption when VBAT = 3.0 V Buck Enabled 0.40 2.71 mA Code executing from flash, cache enabled, peripheral clocks off, HCLK = 6.5 MHz 0.98 1.29 mA Code executing from flash, cache enabled, peripheral clocks off, HCLK = 26 MHz 1.28 1.64 mA Code executing from flash, cache disabled, peripheral clocks off, HCLK = 26 MHz 0.95 1.36 mA Code executing from SRAM, peripheral clocks off, HCLK = 26 MHz 1.08 1.43 mA Code executing from flash, cache enabled, peripheral clocks on, HCLK = 26 MHz, PCLK = 26 MHz 1.37 1.78 mA Code executing from flash, cache disabled, peripheral clocks on, HCLK = 26 MHz, PCLK = 26 MHz 1.08 1.49 mA Code executing from SRAM, peripheral clocks on, HCLK = 26 MHz, PCLK = 26 MHz Dynamic Current 30 µA/MHz Code executing from flash, cache enabled 1.75 8.05 mA Code executing from flash, cache enabled, peripheral clocks off, HCLK = 26 MHz 2.34 3.0 mA Code executing from flash, cache disabled, peripheral clocks off, HCLK = 26 MHz 1.78 2.48 mA Code executing from SRAM, peripheral clocks off, HCLK = 26 MHz 1.99 2.67 mA Code executing from flash, cache enabled, peripheral clocks on, HCLK = 26 MHz, PCLK = 26 MHz 2.55 3.29 mA Code executing from flash, cache disabled, peripheral clocks on, HCLK = 26 MHz, PCLK = 26 MHz 2.03 2.74 mA Code executing from SRAM, peripheral clocks on, HCLK = 26 MHz, PCLK = 26 MHz 60 µA/MHz Code executing from flash, cache enabled 1 TJ = 25°C. 2 TJ = 85°C. 3 The code being executed is a prime number generation in a continuous loop, with HFOSC as the system clock source.
Flexi Mode Table 5. Parameter Min Typ1 Max2 Unit Test Conditions/Comments
FLEXI™ MODE Current consumption when VBAT = 3.0 V Buck Enabled 0.3 0.67 mA Peripheral clocks off 0.39 0.80 mA Peripheral clocks on, PCLK = 26 MHz Buck Disabled 0.52 1.11 mA Peripheral clocks off 0.7 1.38 mA Peripheral clocks on, PCLK = 26 MHz 1 TJ = 25°C. 2 TJ = 85°C. Rev. B | Page 5 of 39 Document Outline Features Applications Functional Block Diagram Revision History General Description Product Highlights Specifications Operating Conditions and Electrical Characteristics Embedded Flash Specifications Power Supply Current Specifications Active Mode Flexi Mode Deep Sleep Modes—VBAT = 3.0 V ADC Specifications System Clocks External Crystal Oscillator Specifications On-Chip RC Oscillator Specifications System Clocks and PLL Specifications Timing Specifications Reset Timing Serial Ports Timing SPI Timing I2C Specifications General-Purpose Port Timing RTC1 (FLEX_RTC) Specifications Timer Pulse-Width Modulation (PWM) Output Cycle Timing Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation ARM Cortex-M3 Processor ARM Cortex-M3 Memory Subsystem Code Region SRAM Region System Region Memory Architecture SRAM Region MMRs (Peripheral Control and Status) Flash Memory Cache Controller System and Integration Features Reset Booting Power Management Power Modes Active Mode Flexi Mode Hibernate Mode Shutdown Mode Security Features Cryptographic Accelerator True Random Number Generator (TRNG) Reliability and Robustness Features ECC Enabled Flash Memory Multiparity Bit Protected SRAM Software Watchdog Cyclic Redundancy Check (CRC) Accelerator Programmable GPIOs Timers General-Purpose Timers Watchdog Timer (WDT) Analog-to-Digital Converter (ADC) Subsystem Clocking Beeper Driver Debug Capability On-Chip Peripheral Features Serial Ports (SPORT) SPI Ports UART Port I2C Development Support Documentation Hardware Software Additional Information Reference Designs MCU Test Conditions Driver Types EEMBC ULPMark™-CP Score GPIO Multiplexing Applications Information About ADuCM3027/ADuCM3029 Silicon Anomalies Functionality Issues Outline Dimensions Ordering Guide