Datasheet ADuCM3027, ADuCM3029 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | Ultra Low Power ARM Cortex-M3 MCU with Integrated Power Management |
| 页数 / 页 | 39 / 10 — ADuCM3027. /ADuCM3029. Data Sheet. DRIVE EDGE. SAMPLE EDGE. tSCLKIW. … |
| 修订版 | B |
| 文件格式/大小 | PDF / 698 Kb |
| 文件语言 | 英语 |
ADuCM3027. /ADuCM3029. Data Sheet. DRIVE EDGE. SAMPLE EDGE. tSCLKIW. SPT0_ACLK/SPT0_BCLK. (SPORT CLOCK). tDFSI. tHOFSI. SPT_0AFS/SPT_0BFS
该数据表的模型线
文件文字版本
ADuCM3027 /ADuCM3029 Data Sheet DRIVE EDGE SAMPLE EDGE tSCLKIW SPT0_ACLK/SPT0_BCLK (SPORT CLOCK) tDFSI tHOFSI SPT_0AFS/SPT_0BFS (FRAME SYNC) tSDRI tHDRI SPT_AD0/SPT_BD0
003
(DATA CHANNEL A/B)
14168- Figure 3. Serial Ports (Data Receive Mode through Internal Clock)
DRIVE EDGE SAMPLE EDGE tSCLKIW SPT0_ACLK/SPT0_BCLK (SPORT CLOCK) tDFSI tHOFSI SPT_0AFS/SPT_0BFS (FRAME SYNC) tDDTI tHDTI SPT_AD0/SPT_BD0
004
(DATA CHANNEL A/B)
14168- Figure 4. Serial Ports (Data Transmit Mode through Internal Clock)
DRIVE EDGE SAMPLE EDGE tSCLKW SPT0_ACLK/SPT0_BCLK (SPORT CLOCK) tDFSE tHOFSE tSFSE tHFSE SPT0_AFS/SPT0_BFS (FRAME SYNC) tSDRE tHDRE SPT0_AD0/SPT0_BD0
005
(DATA CHANNEL A/B)
14168- Figure 5. Serial Ports (Data Receive Mode through External Clock)
DRIVE EDGE SAMPLE EDGE tSCLKW SPT0_ACLK/SPT0_BCLK (SPORT CLOCK) tDFSE t t HOFSE SFSE tHFSE SPT_0AFS/SPT_0BFS (FRAME SYNC) tDDTE tHDTE SPT_AD0/SPT_BD0
006
(DATA CHANNEL A/B)
14168- Figure 6. Serial Ports (Data Transmit Mode through External Clock) Rev. B | Page 10 of 39 Document Outline Features Applications Functional Block Diagram Revision History General Description Product Highlights Specifications Operating Conditions and Electrical Characteristics Embedded Flash Specifications Power Supply Current Specifications Active Mode Flexi Mode Deep Sleep Modes—VBAT = 3.0 V ADC Specifications System Clocks External Crystal Oscillator Specifications On-Chip RC Oscillator Specifications System Clocks and PLL Specifications Timing Specifications Reset Timing Serial Ports Timing SPI Timing I2C Specifications General-Purpose Port Timing RTC1 (FLEX_RTC) Specifications Timer Pulse-Width Modulation (PWM) Output Cycle Timing Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation ARM Cortex-M3 Processor ARM Cortex-M3 Memory Subsystem Code Region SRAM Region System Region Memory Architecture SRAM Region MMRs (Peripheral Control and Status) Flash Memory Cache Controller System and Integration Features Reset Booting Power Management Power Modes Active Mode Flexi Mode Hibernate Mode Shutdown Mode Security Features Cryptographic Accelerator True Random Number Generator (TRNG) Reliability and Robustness Features ECC Enabled Flash Memory Multiparity Bit Protected SRAM Software Watchdog Cyclic Redundancy Check (CRC) Accelerator Programmable GPIOs Timers General-Purpose Timers Watchdog Timer (WDT) Analog-to-Digital Converter (ADC) Subsystem Clocking Beeper Driver Debug Capability On-Chip Peripheral Features Serial Ports (SPORT) SPI Ports UART Port I2C Development Support Documentation Hardware Software Additional Information Reference Designs MCU Test Conditions Driver Types EEMBC ULPMark™-CP Score GPIO Multiplexing Applications Information About ADuCM3027/ADuCM3029 Silicon Anomalies Functionality Issues Outline Dimensions Ordering Guide
003
(DATA CHANNEL A/B)
14168- Figure 3. Serial Ports (Data Receive Mode through Internal Clock)
DRIVE EDGE SAMPLE EDGE tSCLKIW SPT0_ACLK/SPT0_BCLK (SPORT CLOCK) tDFSI tHOFSI SPT_0AFS/SPT_0BFS (FRAME SYNC) tDDTI tHDTI SPT_AD0/SPT_BD0
004
(DATA CHANNEL A/B)
14168- Figure 4. Serial Ports (Data Transmit Mode through Internal Clock)
DRIVE EDGE SAMPLE EDGE tSCLKW SPT0_ACLK/SPT0_BCLK (SPORT CLOCK) tDFSE tHOFSE tSFSE tHFSE SPT0_AFS/SPT0_BFS (FRAME SYNC) tSDRE tHDRE SPT0_AD0/SPT0_BD0
005
(DATA CHANNEL A/B)
14168- Figure 5. Serial Ports (Data Receive Mode through External Clock)
DRIVE EDGE SAMPLE EDGE tSCLKW SPT0_ACLK/SPT0_BCLK (SPORT CLOCK) tDFSE t t HOFSE SFSE tHFSE SPT_0AFS/SPT_0BFS (FRAME SYNC) tDDTE tHDTE SPT_AD0/SPT_BD0
006
(DATA CHANNEL A/B)
14168- Figure 6. Serial Ports (Data Transmit Mode through External Clock) Rev. B | Page 10 of 39 Document Outline Features Applications Functional Block Diagram Revision History General Description Product Highlights Specifications Operating Conditions and Electrical Characteristics Embedded Flash Specifications Power Supply Current Specifications Active Mode Flexi Mode Deep Sleep Modes—VBAT = 3.0 V ADC Specifications System Clocks External Crystal Oscillator Specifications On-Chip RC Oscillator Specifications System Clocks and PLL Specifications Timing Specifications Reset Timing Serial Ports Timing SPI Timing I2C Specifications General-Purpose Port Timing RTC1 (FLEX_RTC) Specifications Timer Pulse-Width Modulation (PWM) Output Cycle Timing Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation ARM Cortex-M3 Processor ARM Cortex-M3 Memory Subsystem Code Region SRAM Region System Region Memory Architecture SRAM Region MMRs (Peripheral Control and Status) Flash Memory Cache Controller System and Integration Features Reset Booting Power Management Power Modes Active Mode Flexi Mode Hibernate Mode Shutdown Mode Security Features Cryptographic Accelerator True Random Number Generator (TRNG) Reliability and Robustness Features ECC Enabled Flash Memory Multiparity Bit Protected SRAM Software Watchdog Cyclic Redundancy Check (CRC) Accelerator Programmable GPIOs Timers General-Purpose Timers Watchdog Timer (WDT) Analog-to-Digital Converter (ADC) Subsystem Clocking Beeper Driver Debug Capability On-Chip Peripheral Features Serial Ports (SPORT) SPI Ports UART Port I2C Development Support Documentation Hardware Software Additional Information Reference Designs MCU Test Conditions Driver Types EEMBC ULPMark™-CP Score GPIO Multiplexing Applications Information About ADuCM3027/ADuCM3029 Silicon Anomalies Functionality Issues Outline Dimensions Ordering Guide