Datasheet ADuCM4050 (Analog Devices) - 9

Data Sheet ADuCM4050 Deep Sleep Modes—VBAT = 3.6 V Table 7. Parameter Min Typ Max Unit Test Conditions/Comments
HIBERNATE MODE1 VBAT = 3.6 V TJ = 25°C 0.66 µA RTC1 and RTC0 disabled, 16 kB SRAM retained, LFXTAL off 0.73 µA RTC1 and RTC0 disabled, 28 kB SRAM retained, LFXTAL off 0.77 µA RTC1 and RTC0 disabled, 48 kB SRAM retained, LFXTAL off 0.82 µA RTC1 and RTC0 disabled, 60 kB SRAM retained, LFXTAL off 1.04 µA RTC1 and RTC0 disabled, 80 kB SRAM retained, LFXTAL off 1.08 µA RTC1 and RTC0 disabled, 92 kB SRAM retained, LFXTAL off 1.12 µA RTC1 and RTC0 disabled, 112 kB SRAM retained, LFXTAL off 1.16 µA RTC1 and RTC0 disabled, 124 kB SRAM retained, LFXTAL off 0.69 µA RTC1 enabled, 16 kB SRAM retained, LFOSC as RTC1 source 1.19 µA RTC1 enabled, 124 kB SRAM retained, LFOSC as RTC1 source 0.85 µA RTC1 enabled, 16 kB SRAM retained, LFXTAL as RTC1 source 0.96 µA RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC0 source 0.98 µA RTC1 and RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC1 and RTC0 source 1.32 µA RTC1 enabled, 124 kB SRAM retained, LFXTAL as RTC1 source 1.43 µA RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC0 source 1.45 µA RTC1 and RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC1 and RTC0 source TJ = 85°C 1.95 5.00 µA RTC1 and RTC0 disabled, 16 kB SRAM retained, LFXTAL off 2.29 6.00 µA RTC1 and RTC0 disabled, 28 kB SRAM retained, LFXTAL off 2.82 7.20 µA RTC1 and RTC0 disabled, 48 kB SRAM retained, LFXTAL off 3.14 8.20 µA RTC1 and RTC0 disabled, 60 kB SRAM retained, LFXTAL off 3.78 10.00 µA RTC1 and RTC0 disabled, 80 kB SRAM retained, LFXTAL off 4.10 11.00 µA RTC1 and RTC0 disabled, 92 kB SRAM retained, LFXTAL off 4.63 12.30 µA RTC1 and RTC0 disabled, 112 kB SRAM retained, LFXTAL off 4.95 14.90 µA RTC1 and RTC0 disabled, 124 kB SRAM retained, LFXTAL off 2.07 5.30 µA RTC1 enabled, 16 kB SRAM retained, LFOSC as RTC1 source 5.06 15.20 µA RTC1 enabled, 124 kB SRAM retained, LFOSC as RTC1 source 2.52 6.19 µA RTC1 enabled, 16 kB SRAM retained, LFXTAL as RTC1 source 2.63 6.48 µA RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC0 source 2.65 6.53 µA RTC1 and RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC1 and RTC0 source 5.51 15.34 µA RTC1 enabled, 124 kB SRAM retained, LFXTAL as RTC1 source 5.62 15.64 µA RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC0 source 5.64 15.71 µA RTC1 and RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC1 and RTC0 source SHUTDOWN MODE1 VBAT = 3.6 V TJ = 25°C 0.07 µA RTC0 disabled 1.05 µA RTC0 enabled, LFXTAL as RTC0 source TJ = 85°C 0.58 1.90 µA RTC0 disabled 1.79 5.57 µA RTC0 enabled, LFXTAL as RTC0 source FAST SHUTDOWN VBAT = 3.6 V MODE1 TJ = 25°C 0.22 µA RTC0 disabled 1.21 µA RTC0 enabled, LFXTAL as RTC0 source TJ = 85°C 0.75 2.10 µA RTC0 disabled 1.97 6.32 µA RTC0 enabled, LFXTAL as RTC0 source 1 Buck enable/disable does not affect power consumption. Rev. A | Page 9 of 46 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTICS EMBEDDED FLASH SPECIFICATIONS POWER SUPPLY CURRENT SPECIFICATIONS Active Mode Flexi Mode Deep Sleep Modes—VBAT = 1.8 V Deep Sleep Modes—VBAT = 3.0 V Deep Sleep Modes—VBAT = 3.6 V ADC SPECIFICATIONS TEMPERATURE SENSOR SPECIFICATIONS SYSTEM CLOCKS External Crystal Oscillator Specifications On-Chip Resistor-Capacitor (RC) Oscillator Specifications System Clocks and Phase-Locked Loop (PLL) Specifications TIMING SPECIFICATIONS Reset Timing Serial Ports Timing SPI Timing I2C Specifications General-Purpose Port Timing RTC1 (FLEX_RTC) Specifications Timer Pulse-Width Modulation (PWM) Output Cycle Timing ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ARM CORTEX-M4F PROCESSOR ARM Cortex-M4F Subsystem Code Region SRAM Region System Region MEMORY ARCHITECTURE SRAM Region MMRs (Peripheral Control and Status) Flash Memory Cache Controller SYSTEM INTEGRATION FEATURES Reset Booting Power Management and Modes Active Mode Flexi Mode Hibernate Mode Shutdown Mode Shutdown Mode—Fast Wake-Up Power Management and Control Security Features Cryptographic Accelerator True Random Number Generator (TRNG) Reliability and Robustness Features ECC Enabled Flash Memory Multiparity Bit Protected SRAM Software Watchdog CRC Accelerator Programmable GPIOs Timers General-Purpose Timers Watchdog Timer (WDT) RGB Timer ADC Subsystem Clocking Clock Fail Detection Real-Time Clock (RTC) Beeper Driver Debug Capability ON-CHIP PERIPHERAL FEATURES Serial Ports (SPORT) SPI Ports UART Ports I2C DEVELOPMENT SUPPORT Documentation Hardware Software REFERENCE DESIGNS SECURITY FEATURES DISCLAIMER MCU TEST CONDITIONS DRIVER TYPES EEMBC ULPMARK™-CP SCORE GPIO MULTIPLEXING APPLICATIONS INFORMATION SILICON ANOMALY ADuCM4050 FUNCTIONALITY ISSUES FUNCTIONALITY ISSUES SECTION 1. ADuCM4050 FUNCTIONALITY ISSUES OUTLINE DIMENSIONS ORDERING GUIDE