Datasheet ADuCM4050 (Analog Devices) - 3

Data Sheet ADuCM4050 GENERAL DESCRIPTION
The ADuCM4050 microcontroller unit (MCU) is an ultra low The ADuCM4050 features a real-time clock (RTC), general- power integrated microcontrol er system with integrated power purpose and watchdog timers, and programmable general-purpose management for processing, control, and connectivity. The MCU input/output (GPIO) pins. There is a hardware cyclic redundancy system is based on the ARM® Cortex®-M4F processor. The check (CRC) calculator with programmable generator polynomial. MCU also has a collection of digital peripherals, embedded The device also features a power on reset (POR) and power supply static random access memory (SRAM) and embedded flash monitor (PSM), a 12-bit successive approximation register (SAR) memory, and an analog subsystem that provides clocking, reset, ADC, a red/green/blue (RGB) timer for driving RGB LED, and a and power management capabilities in addition to an analog- true random number generator (TRNG). to-digital converter (ADC) subsystem. To support low dynamic and hibernate power management, the This data sheet describes the ARM Cortex-M4F core and ADuCM4050 MCU provides a col ection of power modes and memory architecture used on the ADuCM4050 MCU. It does features such as dynamic- and software-controlled clock gating not provide detailed programming information about the ARM and power gating. processor. For ful details on the ADuCM4050 MCU, refer to the The system features include an up to 52 MHz ARM Cortex- ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with M4F processor, 512 kB of embedded flash memory with error Integrated Power Management Hardware Reference. correction code (ECC), an optional 4 kB cache for lower active
PRODUCT HIGHLIGHTS
power, and 128 kB system SRAM with parity. The ADuCM4050 features a power management unit (PMU), multilayer advanced 1. Ultra low power consumption. microcontroller bus architecture (AMBA) bus matrix, central 2. Robust operation. direct memory access (DMA) controller, and beeper interface. 3. Ful voltage monitoring in deep sleep modes. 4. ECC support on flash. The ADuCM4050 features cryptographic hardware supporting 5. Parity error detection on SRAM memory. advanced encryption standard (AES)-128 and AES-256 with 6. Leading edge security. secure hash algorithm (SHA)-256 and the following modes: 7. Fast encryption provides read protection to user algorithms. electronic code book (ECB), cipher block chaining (CBC), 8. Write protection prevents device reprogramming by counter (CTR), and cipher block chaining-message unauthorized code. authentication code (CCM/CCM*) modes. 9. Failure detection of 32 kHz low frequency external crystal The ADuCM4050 has protected key storage with key wrap/ oscil ator (LFXTAL) via interrupt. unwrap, and keyed hashed message authentication code (HMAC) 10. SensorStrobe™ for precise time synchronized sampling of with key unwrap. external sensors. Works in hibernate mode, resulting in drastic The ADuCM4050 supports serial port (SPORT), serial peripheral current reduction in system solutions. Current consumption interface (SPI), I2C, and universal asynchronous receiver/ reduces by 10 times when using, for example, the ADXL363 transmitter (UART) peripheral interfaces. accelerometer. Software intervention is not required after setup. No pulse drift due to software execution. Rev. A | Page 3 of 46 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTICS EMBEDDED FLASH SPECIFICATIONS POWER SUPPLY CURRENT SPECIFICATIONS Active Mode Flexi Mode Deep Sleep Modes—VBAT = 1.8 V Deep Sleep Modes—VBAT = 3.0 V Deep Sleep Modes—VBAT = 3.6 V ADC SPECIFICATIONS TEMPERATURE SENSOR SPECIFICATIONS SYSTEM CLOCKS External Crystal Oscillator Specifications On-Chip Resistor-Capacitor (RC) Oscillator Specifications System Clocks and Phase-Locked Loop (PLL) Specifications TIMING SPECIFICATIONS Reset Timing Serial Ports Timing SPI Timing I2C Specifications General-Purpose Port Timing RTC1 (FLEX_RTC) Specifications Timer Pulse-Width Modulation (PWM) Output Cycle Timing ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ARM CORTEX-M4F PROCESSOR ARM Cortex-M4F Subsystem Code Region SRAM Region System Region MEMORY ARCHITECTURE SRAM Region MMRs (Peripheral Control and Status) Flash Memory Cache Controller SYSTEM INTEGRATION FEATURES Reset Booting Power Management and Modes Active Mode Flexi Mode Hibernate Mode Shutdown Mode Shutdown Mode—Fast Wake-Up Power Management and Control Security Features Cryptographic Accelerator True Random Number Generator (TRNG) Reliability and Robustness Features ECC Enabled Flash Memory Multiparity Bit Protected SRAM Software Watchdog CRC Accelerator Programmable GPIOs Timers General-Purpose Timers Watchdog Timer (WDT) RGB Timer ADC Subsystem Clocking Clock Fail Detection Real-Time Clock (RTC) Beeper Driver Debug Capability ON-CHIP PERIPHERAL FEATURES Serial Ports (SPORT) SPI Ports UART Ports I2C DEVELOPMENT SUPPORT Documentation Hardware Software REFERENCE DESIGNS SECURITY FEATURES DISCLAIMER MCU TEST CONDITIONS DRIVER TYPES EEMBC ULPMARK™-CP SCORE GPIO MULTIPLEXING APPLICATIONS INFORMATION SILICON ANOMALY ADuCM4050 FUNCTIONALITY ISSUES FUNCTIONALITY ISSUES SECTION 1. ADuCM4050 FUNCTIONALITY ISSUES OUTLINE DIMENSIONS ORDERING GUIDE