Datasheet ADuCM4050 (Analog Devices) - 4

制造商Analog Devices
描述Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management
页数 / 页46 / 4 — ADuCM4050. Data Sheet. SPECIFICATIONS OPERATING CONDITIONS AND ELECTRICAL …
修订版A
文件格式/大小PDF / 754 Kb
文件语言英语

ADuCM4050. Data Sheet. SPECIFICATIONS OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTICS. Table 1. Parameter. Symbol. Min. Typ. Max

ADuCM4050 Data Sheet SPECIFICATIONS OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTICS Table 1 Parameter Symbol Min Typ Max

该数据表的模型线

文件文字版本

ADuCM4050 Data Sheet SPECIFICATIONS OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTICS Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
EXTERNAL BATTERY SUPPLY VOLTAGE1, 2 VBAT 1.74 3.0 3.6 V INPUT VOLTAGE High Level VIH 2.5 V VBAT = 3.6 V Low Level VIL 0.45 V VBAT = 1.74 V ADC SUPPLY VOLTAGE VBAT_ADC 1.74 3.0 3.6 V OUTPUT VOLTAGE3 High Level VOH 1.4 V VBAT = 1.74 V, IOH = −1.0 mA Low Level VOL 0.4 V VBAT = 1.74 V, IOL = 1.0 mA INPUT CURRENT PULL-UP4 High Level IIHPU 0.01 0.2 µA VBAT = 3.6 V, VIN = 3.6 V Low Level IILPU 100 µA VBAT = 3.6 V, VIN = 0 V THREE-STATE LEAKAGE CURRENT High Level5 IOZH 0.01 0.15 µA VBAT = 3.6 V, VIN = 3.6 V Pull-Up6 IOZHPU 0.30 µA VBAT = 3.6 V, VIN = 3.6 V Pull-Down7 IOZHPD 100 µA VBAT = 3.6 V, VIN = 3.6 V Low Level5 IOZL 0.01 0.15 µA VBAT = 3.6 V, VIN = 0 V Pull-Up6 IOZLPU 100 µA VBAT = 3.6 V, VIN = 0 V Pull-Down7 IOZLPD 0.15 µA VBAT = 3.6 V, VIN = 0 V INPUT CAPACITANCE CIN 10 pF TJ = 25°C VBAT POWER-ON RESET VVBAT_POR 1.49 1.59 1.64 V Power-on reset level on VBAT; trip point is detected when battery is decaying8 Junction Temperature TJ −40 +85 °C TAMBIENT = −40°C to +85°C 1 Value applies to VBAT_ANA1, VBAT_ANA2, VBAT_DIG1, and VBAT_DIG2 pins. 2 Must remain powered (even if the associated function is not used). 3 Applies to the output and bidirectional pins: P0_00 to P0_15, P1_00 to P1_15, P2_00 to P2_15, and P3_00 to P3_03. 4 Applies to the SYS_HWRST input pin with pull-up. 5 Applies to the three-state pins: P0_00 to P0_05, P0_08 to P0_15, P1_00 to P1_15, P2_00 to P2_15, P3_00 to P3_03. 6 Applies to the three-state pins with pull-ups: P0_00 to P0_05, P0_07 to P0_15, P1_00 to P1_15, P2_00 to P2_15, and P3_00 to P3_03. 7 Applies to the P0_06 three-state pin with pull-down. 8 This specification is valid when the device is powered up; if the battery decays and falls below 1.71 V, power-on reset is detected. For safer operation of the device, adhere to the VBAT specification.
EMBEDDED FLASH SPECIFICATIONS Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
FLASH Endurance 10,000 Cycles Data Retention 10 Years Rev. A | Page 4 of 46 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTICS EMBEDDED FLASH SPECIFICATIONS POWER SUPPLY CURRENT SPECIFICATIONS Active Mode Flexi Mode Deep Sleep Modes—VBAT = 1.8 V Deep Sleep Modes—VBAT = 3.0 V Deep Sleep Modes—VBAT = 3.6 V ADC SPECIFICATIONS TEMPERATURE SENSOR SPECIFICATIONS SYSTEM CLOCKS External Crystal Oscillator Specifications On-Chip Resistor-Capacitor (RC) Oscillator Specifications System Clocks and Phase-Locked Loop (PLL) Specifications TIMING SPECIFICATIONS Reset Timing Serial Ports Timing SPI Timing I2C Specifications General-Purpose Port Timing RTC1 (FLEX_RTC) Specifications Timer Pulse-Width Modulation (PWM) Output Cycle Timing ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ARM CORTEX-M4F PROCESSOR ARM Cortex-M4F Subsystem Code Region SRAM Region System Region MEMORY ARCHITECTURE SRAM Region MMRs (Peripheral Control and Status) Flash Memory Cache Controller SYSTEM INTEGRATION FEATURES Reset Booting Power Management and Modes Active Mode Flexi Mode Hibernate Mode Shutdown Mode Shutdown Mode—Fast Wake-Up Power Management and Control Security Features Cryptographic Accelerator True Random Number Generator (TRNG) Reliability and Robustness Features ECC Enabled Flash Memory Multiparity Bit Protected SRAM Software Watchdog CRC Accelerator Programmable GPIOs Timers General-Purpose Timers Watchdog Timer (WDT) RGB Timer ADC Subsystem Clocking Clock Fail Detection Real-Time Clock (RTC) Beeper Driver Debug Capability ON-CHIP PERIPHERAL FEATURES Serial Ports (SPORT) SPI Ports UART Ports I2C DEVELOPMENT SUPPORT Documentation Hardware Software REFERENCE DESIGNS SECURITY FEATURES DISCLAIMER MCU TEST CONDITIONS DRIVER TYPES EEMBC ULPMARK™-CP SCORE GPIO MULTIPLEXING APPLICATIONS INFORMATION SILICON ANOMALY ADuCM4050 FUNCTIONALITY ISSUES FUNCTIONALITY ISSUES SECTION 1. ADuCM4050 FUNCTIONALITY ISSUES OUTLINE DIMENSIONS ORDERING GUIDE